Processing-in-Memory (PIM) DRAM Market

Key Statistics

Processing-in-Memory (PIM) DRAM Market Overview

Processing-in-memory (PIM) DRAM market was valued at USD 2,140 million in 2026 and is projected to reach USD 14,464 million by 2036, expanding at a CAGR of 21.1% over 2027–2036. The leading region is Asia-Pacific, with an estimated ~51% of 2026 revenue, supported by memory development and manufacturing in South Korea and surrounding semiconductor supply chains.

Base year: 2026 · Estimated year: 2027 · Forecast period: 2027–2036 · Historical data: 2021–2025 · Values in USD million

Processing-in-memory changes the location of selected calculations rather than merely increasing DRAM bandwidth. Traditional systems repeatedly fetch operands from memory into a CPU or GPU, process them, and write results back. PIM places specialized arithmetic closer to DRAM arrays or in a module-side buffer, reducing traffic across the memory interface for suitable operations. The distinction is important because a conventional high-bandwidth memory stack can move data quickly without performing arithmetic within the memory device. The revenue boundary here covers PIM-enabled DRAM devices and memory modules, not the complete servers into which they are installed.

Samsung introduced HBM-PIM in February 2021 by embedding an AI processing engine within HBM2 memory banks, reporting more than twice the system performance and over 70% lower energy consumption for its demonstrated workloads. Later integration with a Xilinx Alveo accelerator showed a different workload configuration with a 2.5-fold system improvement and a reduction in energy consumption exceeding 60%. These figures are demonstration-specific and should not be generalized to all data-center applications. They nevertheless show why a memory product carrying useful arithmetic capability can command attention beyond ordinary DRAM price-per-bit comparisons.

SK hynix pursued a distinct route with GDDR6-AiM, announced in February 2022, and subsequently displayed AiMX accelerator cards containing multiple AiM chips. A September 2024 demonstration used a 32 GB prototype and Llama 3 70B workloads to examine memory-intensive inference. The card provides useful evidence that memory-side computation can support real software workloads, but revenue for the card, GPUs and complete servers is outside the PIM DRAM device market. The commercially relevant question is how much of the hardware value resides in the specialized memory components rather than in the assembled accelerator.

The modeled 2026 type mix assigns ~40% to HBM-PIM, ~20% to GDDR-PIM, ~18% to LPDDR-PIM, ~14% to near-memory computing DRAM and ~8% to HMC PIM. Those percentages describe an estimated distribution within the defined market, not disclosed manufacturer shipments. By architecture, near-memory processing is modeled at ~45%, true in-memory processing at ~39% and computational DRAM at ~16%. Differences in programming support, thermal limits and host compatibility make it unlikely that all architectures will commercialize at the same pace.

Demand has a broader infrastructure backdrop but must be interpreted carefully. The U.S. Department of Energy reported that data centers consumed 176 TWh in 2023 and projected 325–580 TWh in 2028, while a Lawrence Berkeley National Laboratory update issued in June 2026 explored 2030 consumption scenarios. These energy figures demonstrate pressure to reduce data movement and power use, but they do not measure PIM device sales. Adoption depends on measurable end-to-end cost and latency improvements, compiler support and the willingness of hyperscalers to qualify a new memory architecture alongside existing GPUs and HBM.

Segment Analysis: By Type

The type taxonomy separates HBM-PIM, LPDDR-PIM, GDDR-PIM, HMC PIM and near-memory computing DRAM. HBM-PIM leads with an estimated ~40% in 2026, while LPDDR-PIM is modeled to grow at ~23.5% annually as device-side AI broadens. These are separate memory-device and module categories, not a count of accelerator cards or conventional DRAM shipments. For the type mix, purchasing decisions also depend on workload fit, system validation, software support and sustained access to qualified memory supply. For the type mix, the distinction between memory-component value and the price of an integrated accelerator remains essential when comparing deployments across customer groups and geographies.

High Bandwidth Memory PIM (HBM-PIM)

High Bandwidth Memory PIM (HBM-PIM) serves memory-intensive ai inference and supercomputing through bank-level arithmetic integrated with stacked high-bandwidth memory. Its modeled ~40% share in 2026 reflects the relative maturity of demonstrations, addressable workloads and memory-system integration. Samsung HBM2 Aquabolt-XL demonstration and accelerator integration provides the principal product or development reference. Qualification remains demanding because thermal budget and software portability can eliminate benefits observed in a narrowly optimized benchmark.

LPDDR-PIM

LPDDR-PIM serves handsets, embedded ai and battery-limited inference through low-power dram incorporating operations close to mobile data. Its modeled ~18% share in 2026 reflects the relative maturity of demonstrations, addressable workloads and memory-system integration. Samsung mobile-memory direction and SK hynix on-device AiM roadmap provides the principal product or development reference. Qualification remains demanding because power envelope, die area and mobile software can eliminate benefits observed in a narrowly optimized benchmark.

GDDR-PIM

GDDR-PIM serves attention acceleration and memory-bound model serving through graphics-class dram enhanced with processing elements. Its modeled ~20% share in 2026 reflects the relative maturity of demonstrations, addressable workloads and memory-system integration. SK hynix GDDR6-AiM and AiMX demonstrations provides the principal product or development reference. Qualification remains demanding because host integration and specialized operator support can eliminate benefits observed in a narrowly optimized benchmark.

Hybrid Memory Cube (HMC) PIM

Hybrid Memory Cube (HMC) PIM serves hpc and bandwidth-sensitive graph processing through memory-stack architectures with near-vault logic capability. Its modeled ~8% share in 2026 reflects the relative maturity of demonstrations, addressable workloads and memory-system integration. Research prototypes rather than broadly confirmed volume products provides the principal product or development reference. Qualification remains demanding because packaging cost and limited ecosystem standardization can eliminate benefits observed in a narrowly optimized benchmark.

Near-Memory Computing DRAM

Near-Memory Computing DRAM serves data analytics and enterprise servers through dram modules or memory subsystems with adjacent compute. Its modeled ~14% share in 2026 reflects the relative maturity of demonstrations, addressable workloads and memory-system integration. Samsung AXDIMM and other module-side processing approaches provides the principal product or development reference. Qualification remains demanding because qualification and distinction from standalone accelerator cards can eliminate benefits observed in a narrowly optimized benchmark.

Segment Analysis: By Application

AI and machine learning are the largest application group, with an estimated ~45% of 2026 PIM DRAM revenue, followed by HPC at ~23%, data analytics at ~15%, graph and database acceleration at ~11%, and other applications at ~6%. The commercial case is strongest where moving operands consumes more energy or time than the arithmetic itself.

The five application groups share a dependence on repeatable, memory-bound operations, but they differ in tolerance for specialized kernels. Inference services often prioritize latency and energy per generated token; HPC users require numerical reproducibility and toolchain continuity; database operators emphasize predictable cost per query. This separation explains why successful PIM demonstrations do not automatically translate into uniform adoption across all workloads.

Regional Analysis

Asia-Pacific leads the global PIM DRAM market at an estimated ~51% of 2026 revenue, reflecting memory-device development and production in South Korea. North America follows at ~24%, Europe at ~17%, the Middle East and Africa at ~5%, and South America at ~3%. These allocations are modeled estimates rather than observed geographic shipments, and they describe component revenue within the defined PIM-enabled memory boundary.

How does regional PIM DRAM demand differ across production centers and end users?

The location of memory-device engineering does not always match the location of the final accelerator user. Asia-Pacific has the strongest production and demonstration base, while North America concentrates cloud inference demand and Europe has visible specialist PIM development. Emerging markets are more likely to enter through imported accelerator platforms and research systems. Regional revenue therefore depends on the place of component consumption, qualified supply relationships and whether specialized memory is actually included in shipped hardware.

Competitive Landscape of the Processing-in-Memory DRAM Market

The competitive landscape combines memory manufacturers demonstrating device-side arithmetic with specialist module developers, software and processor ecosystems, and design-tool providers. Samsung and SK hynix have publicly documented PIM memory demonstrations, while UPMEM represents a specialist module approach. Other profiled companies influence architectures or enabling technologies, but their inclusion does not establish direct commercial shipments of PIM DRAM devices.

Samsung has demonstrated HBM-PIM and AXDIMM, linking bank-level processing and module-buffer approaches to accelerator workloads. Its February and August 2021 announcements show different integration routes and reported workload-specific energy benefits. The decisive competitive challenge is converting those evaluations into memory products with repeatable supply, accepted toolchains and durable host support. Ordinary HBM shipments cannot be counted as PIM sales simply because they originate from a supplier that also researches PIM.

SK hynix announced GDDR6-AiM in 2022 and later used AiMX prototypes to demonstrate model inference with memory-side operations. The 2024 32 GB prototype and the 2025 OCP demonstration are evidence of technical progression rather than proof that every system using the company’s GDDR or HBM products contains compute-capable DRAM. Competition therefore hinges on whether a memory device can deliver an economic advantage after accounting for the full system software and validation effort.

The wider company roster includes processor designers, memory suppliers, EDA vendors and IP providers that may support research, integration or qualification. Their roles are not interchangeable with dedicated PIM DRAM manufacturing. A practical competitive comparison separates direct memory-device demonstrations from module-level products and adjacent compute or design infrastructure, then examines memory density, effective bandwidth, programming access, thermal behavior and the evidence behind each claimed application benefit.

Tier structure

Key companies profiled

• Samsung Electronics Co., Ltd.
• SK Hynix Inc.
• Micron Technology, Inc.
• UPMEM SAS
• Intel Corporation
• IBM Corporation
• Alibaba DAMO Academy
• Qualcomm Technologies, Inc.
• NVIDIA Corporation
• AMD (Advanced Micro Devices, Inc.)
• Tsinghua Unigroup (CXMT)
• Synopsys, Inc.
• Cadence Design Systems, Inc.
• Rambus Inc.
• Movellus Circuits Inc.

PIM DRAM Production and Qualification Analysis

Manufacturing PIM DRAM requires conventional memory-process yield alongside additional logic, test and integration requirements. A chip that combines storage and arithmetic must maintain retention, refresh, reliability and thermal behavior while exposing useful operations to the host. This makes qualification more demanding than a benchmark demonstration and favors companies that can coordinate memory design, packaging, firmware and software validation.

Samsung’s bank-integrated HBM-PIM approach places processing close to the DRAM arrays within a stacked-memory product, which raises questions about die area, memory-cell reliability and the available thermal envelope. HBM already relies on complex packaging and high-bandwidth interconnects, so adding useful logic must deliver enough system benefit to justify added manufacturing and validation complexity. Customers assess throughput under representative kernels, not just raw operations per second, and require predictable behavior across memory capacities and accelerator configurations.

SK hynix GDDR6-AiM takes advantage of a graphics-memory form factor familiar to accelerator developers, while AiMX demonstrates how several such chips can operate in a coordinated system. Productizing the memory component still requires controller interfaces, scheduling, error handling and reproducible workloads. A complete AiMX board also contains non-memory hardware, and the value of that assembly is not included in this memory-device market. The separation avoids double counting when analyzing semiconductor revenue and downstream accelerator shipments.

Near-memory module approaches place computation in or near the module buffer instead of inside each DRAM bank. This can simplify some device integration but introduces a different set of controller, interface and software challenges. Research on dynamic allocation for PIM architectures, including PIM-malloc, shows that programming infrastructure remains material to performance. In practice, suppliers must prove consistent benefits across workloads while providing compilers, runtime libraries and diagnostics that enterprise customers can support over several hardware generations.

Processing-in-Memory DRAM Market Dynamics

The main demand forces are growth in memory-bound AI inference, electricity and cooling pressure in data centers, and improvements in PIM software integration. Those forces are offset by qualification risk, limited portable programming tools, and the cost of adding logic to specialized DRAM. The modeled net growth rate reflects both sides of that equation and assumes that PIM devices remain a specialized portion of total DRAM rather than replacing conventional memory across every workload.

MARKET DRIVERS

Drivers Impact Analysis*

Memory-bound inference favors local arithmetic

Attention and repeated parameter reads can be limited by memory transfers rather than arithmetic throughput. SK hynix demonstrated AiMX with large language models, including a 70-billion-parameter Llama 3 configuration in 2024, to show the potential for specialized memory-side operations. These workloads create an addressable segment for PIM DRAM when the memory component can execute supported operations efficiently and the host software can route those operations without excessive overhead.

Electricity pressure rewards avoided data movement

The U.S. Department of Energy estimated 176 TWh of data-center electricity consumption in 2023 and projected 325–580 TWh for 2028. These figures do not measure PIM sales, but they frame why operators examine the energy cost of moving operands between processors and memory. Samsung’s HBM-PIM demonstrations reported large energy reductions on selected workloads; commercial adoption requires customers to reproduce savings in their own system power budgets.

Memory architectures gain more integration options

Samsung explored HBM-PIM and AXDIMM, while SK hynix developed GDDR6-AiM and showed its integration within AiMX. The variety matters because no single memory form factor suits cloud accelerators, mobile devices and scientific computing equally well. A broader set of interfaces can help vendors match arithmetic placement to power, bandwidth and capacity requirements, although each route carries separate testing and software costs.

HPC and graph analytics expose bandwidth bottlenecks

Scientific applications and graph workloads often make irregular accesses that waste energy and stall processors. PIM-malloc research, submitted in May 2025 and revised in January 2026, investigated dynamic allocation on actual PIM hardware and reported substantial allocator-level improvements. Such work illustrates the importance of runtime design in addition to semiconductor performance. HPC institutions will adopt memory-side processing selectively where numerical behavior and software portability meet project requirements.

Software tools make prototypes usable

Compiler passes, kernel libraries, profilers and allocation mechanisms determine whether developers can exploit memory-side compute without rewriting entire applications. Early PIM hardware has often relied on specialized programming paths, which limits the addressable market. Improving these interfaces could expand demand from research demonstrations to repeatable enterprise workloads, provided the resulting software stack supports debugging, security and long-term maintenance across hardware revisions.

MARKET RESTRAINTS

Restraints Impact Analysis*

Programming friction slows deployment

A PIM chip can demonstrate fast arithmetic while still requiring extensive application changes. Data layout, synchronization, memory allocation and operator selection may be different from conventional CPU or GPU programming. The PIM-malloc study demonstrates that even dynamic memory management can become a specialized engineering task. Enterprises therefore evaluate the full cost of porting and supporting software, not just the speed of a single kernel, before committing to production hardware.

Device qualification increases cost and time

Combining logic with DRAM introduces extra validation for refresh behavior, error handling, thermal constraints and yield. HBM-PIM adds these concerns to already complex stacked-memory assembly, while GDDR-PIM and module-level approaches face different interface and controller requirements. A manufacturer must prove repeatable behavior across lots and configurations, and buyers may require long support periods. Those obligations can delay adoption even when laboratory demonstrations show compelling energy or latency results.

Economic gains vary by workload

Not every workload is memory-bound, and many operations benefit more from highly optimized GPUs or CPUs than from moving computation into memory. The relative advantage depends on data reuse, operator availability, batching, software overhead and system utilization. If specialized DRAM costs more but accelerates only a narrow fraction of application time, the total system cost may not improve. Procurement teams consequently test representative workloads before assigning value to a PIM feature.

MARKET OPPORTUNITIES

Inference acceleration for long-context AI

Long-context model serving repeatedly accesses attention state and key-value caches, creating a potential role for memory-side arithmetic. SK hynix used AiMX demonstrations to explore attention-heavy inference with large models, providing a technical example of the opportunity. Suppliers that support stable operators and host integration could sell specialized DRAM into inference platforms, provided the benefit persists under real concurrency, latency and power constraints rather than only on isolated test cases.

Low-power embedded and mobile intelligence

Mobile and edge devices face strict energy and thermal budgets, which can make avoiding off-chip transfers valuable. Samsung discussed extending PIM beyond HBM into mobile memory, while SK hynix outlined on-device AiM directions during its 2024 demonstrations. The opportunity depends on fitting useful arithmetic into low-power DRAM without unacceptable silicon area or battery penalties. Adoption is likely to favor well-defined inference functions over general-purpose computation at first.

Enterprise database and graph operators

Database scans, filtering and graph traversal can require many reads relative to arithmetic work. Moving selected operators close to stored data may reduce interface traffic, but the economics depend on whether the software can schedule those operations efficiently. Research on PIM memory allocators demonstrates that infrastructure such as allocation and runtime coordination matters. Vendors that package supported database primitives and debugging tools can reduce the burden of integrating PIM into existing analytics systems.

European specialist memory-module ecosystems

The European Chips Act supports semiconductor research, pilot lines and supply resilience, creating an environment for specialist memory and compute design. France-based UPMEM represents a distinct module-level PIM approach that can be explored alongside large memory manufacturers. Funding and research initiatives alone do not prove commercial device revenue, but they can help establish software expertise and test facilities that are needed before repeatable deployments can scale.

Processing-in-Memory DRAM Supply Chain Analysis

The PIM DRAM supply chain begins with memory architecture and circuit design, moves through DRAM wafer fabrication and specialized packaging, and ends with accelerator or server qualification. Software tooling is a parallel requirement rather than an optional accessory, because memory-side arithmetic must be invoked and scheduled by applications. Value attribution follows the PIM-enabled memory device or module, excluding the rest of the accelerator board and general-purpose DRAM products.

Upstream. Memory manufacturers need DRAM cell technology, peripheral logic, circuit simulation and packaging expertise. HBM-PIM and GDDR-AiM demonstrate different balances between compute placement and available bandwidth. EDA and IP suppliers support design workflows, but their software or IP sales are not PIM DRAM component revenue. The critical sourcing question is whether a supplier can maintain reliable memory behavior while adding useful processing operations without losing too much density or yield.

Manufacturing. PIM-enabled DRAM requires additional logic and testing beyond ordinary memory production. Stacked HBM packages have different assembly constraints from graphics DRAM and module-buffer architectures, so manufacturing pathways are not interchangeable. Yield, thermal control and error management shape usable supply. Manufacturers must also coordinate device firmware and controller behavior, because a memory product that works in isolation may fail to deliver value when integrated into a real accelerator.

Distribution. PIM devices typically reach customers through semiconductor procurement and platform qualification rather than consumer retail channels. Hyperscalers and hardware OEMs require predictable capacity, long-term supply, compatible controllers and supported software kernels. A demonstration card can establish feasibility but does not establish a separate memory-component sales channel. Supplier contracts must specify which functions reside in the DRAM, which remain on the host and how support responsibilities are divided.

Downstream. AI model serving, HPC research and analytics create distinct downstream demand patterns. Inference buyers evaluate energy per query and latency under concurrent workloads; scientific users emphasize reproducibility and numerical accuracy; database operators prioritize predictable throughput on irregular accesses. These needs determine which PIM architectures can move beyond prototype evaluation. Component demand expands only when customers adopt qualified memory devices or modules, not merely when they announce larger conventional AI data centers.

Recent Developments in the Processing-in-Memory DRAM Market

• 17 February 2021 Announced
  Samsung introduced HBM-PIM using processing engines embedded in HBM2 memory banks. The company described workload-specific performance above 2 times and energy reductions exceeding 70%, establishing a practical demonstration of computation inside memory rather than faster memory transport alone. The significance for future product development was the integration of memory and logic while maintaining an accelerator-compatible interface. Source
• 24 August 2021 Demonstrated
  Samsung described HBM-PIM integration with a Xilinx Alveo accelerator and reported up to 2.5 times system performance with energy savings exceeding 60% for the tested workload. It also introduced AXDIMM, which moves processing into a DRAM-module buffer. The two approaches demonstrate distinct architectures, so their claimed benefits should not be combined into a single universal PIM efficiency figure. Source
• 16 February 2022 Announced
  SK hynix announced GDDR6-AiM, adding computing functions to graphics DRAM to reduce transfers between memory and external processors. Its stated voltage and power comparisons relate to specific configurations and should be read as product-development evidence rather than a measured market-wide efficiency gain. The announcement broadened PIM design choices beyond stacked HBM into a graphics-memory form factor. Source
• 6 December 2022 Partnered
  Samsung and NAVER announced a collaboration on AI-oriented semiconductors that included processing-in-memory and processing-near-memory technologies. The partners described work on large AI models and memory bottlenecks, connecting specialized memory research with real software requirements. This development matters because hardware improvements alone cannot unlock PIM value without compiler, algorithm and platform coordination. Source
• 18 September 2023 Demonstrated
  SK hynix presented the AiMX prototype accelerator card built around multiple GDDR6-AiM devices, using a generative AI model to illustrate memory-side processing. The system demonstration showed the role of supporting controllers and software but did not convert complete accelerator-card value into memory-device sales. It advanced customer understanding of how specialized DRAM might contribute to inference performance. Source
• 13 September 2024 Demonstrated
  SK hynix showed a 32 GB AiMX prototype during the AI Hardware & Edge AI Summit, including a Llama 3 70B model demonstration. The increased memory capacity and attention-oriented workload indicated continued development of practical PIM integration. Prototype capacity should not be mistaken for a disclosed production shipment count; the significance is the technical direction of memory-bound model serving. Source
• 19 May 2025 Published
  Researchers released the PIM-malloc study on dynamic allocation for processing-in-memory hardware, later revised in January 2026. The work reported allocator-level improvements on real PIM devices and highlighted software infrastructure as a limiting factor. This development expands the engineering discussion from raw device bandwidth to programmability, which is essential for applications that allocate memory dynamically. Source
• 31 October 2025 Showcased
  SK hynix displayed AiMX alongside advanced HBM and DRAM products at the 2025 OCP Global Summit. Its demonstration involved GDDR6-AiM chips and attention-heavy model inference with multiple accelerator components. The event reinforced the distinction between compute-capable memory devices and surrounding GPU or card hardware, while showing how PIM research is being evaluated within contemporary data-center systems. Source

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