Key Statistics
Key Takeaways
- PCIe 3.0 remains the largest installed-generation segment in the source scope, but value growth is shifting toward PCIe 5.0 and PCIe 6.0 as AI servers, storage platforms and accelerators need more bandwidth.
- SSD and server applications account for the majority of demand because PCIe switches fan out CPU root complexes to NVMe drives, GPUs, NICs and accelerators inside high-performance systems.
- China is the largest country market in the source dataset, while North America remains the principal innovation and early-adoption hub for hyperscale AI and cloud architectures.
- AI infrastructure is the strongest demand driver: current reference architectures use multiple Gen5 x16 links and PCIe switches to balance GPUs, storage and network devices across CPU root complexes.
- Signal integrity, power and thermal design become more difficult with each PCIe generation, raising development cost and making interoperability testing a central purchasing criterion.
- CXL convergence expands the role of switch silicon from I/O fanout toward memory pooling, resource disaggregation and composable infrastructure.
PCIe Switch Chips Market Overview
PCIe Switch Chips Market is rebased from published anchors of USD 845 million in 2024 and USD 1,955 million in 2032. The resulting series places the market at USD 938 million in 2025, USD 1.04 billion in 2026 and USD 2.41 billion by 2034, equal to an anchor-implied 11.1% CAGR for 2026–2034. China is the largest country market in the published dataset.
PCIe switch chips are packet-switching devices that expand one or more PCI Express root-complex connections into multiple downstream ports and endpoints. They are used where CPUs do not have enough native lanes, where multiple hosts must share devices, or where a system needs topology control, non-transparent bridging, peer-to-peer traffic, hot-plug behavior, telemetry and fault isolation. Typical endpoints include GPUs, AI accelerators, NVMe SSDs, NICs, DPUs and storage controllers.
The market is moving through a generational transition. PCIe 5.0 operates at 32 GT/s per lane, while PCIe 6.0 doubles the rate to 64 GT/s and introduces PAM4 signaling, Forward Error Correction and Flit-mode encoding. PCI-SIG released PCIe 7.0 in June 2025 at 128 GT/s. These transitions increase the value of high-lane-count switch silicon but also raise PHY complexity, package power, validation effort and board-level signal-integrity requirements.
Demand is increasingly shaped by AI and composable infrastructure. NVIDIA’s current reference architecture specifies Gen5 x16 connectivity and PCIe switches where fanout is required to connect GPUs, NVMe devices and network adapters under balanced CPU root complexes. CXL, which uses the PCIe physical layer, extends the opportunity into coherent memory expansion, pooling and device sharing.
Segment Analysis: By Type
By generation, the market is segmented into PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0 and PCIe 6.0. PCIe 3.0 retains the largest installed base in the source scope, while PCIe 5.0 is the current high-volume growth platform and PCIe 6.0 is entering early deployment for AI infrastructure.
| Type | Technical position | Market position |
|---|---|---|
| PCIe 2.0 | 5 GT/s per lane; legacy packet-switch deployments in industrial, embedded and long-life systems. | A declining but persistent installed-base segment where redesign costs and long product lifecycles outweigh bandwidth needs. |
| PCIe 3.0 | 8 GT/s per lane with broad ecosystem maturity and low implementation risk. | The largest installed-generation segment in the source scope. Demand remains substantial in enterprise, industrial and cost-sensitive systems. |
| PCIe 4.0 | 16 GT/s per lane; widely used in contemporary servers, storage and embedded computing. | A mainstream transition platform with broad availability and strong demand in NVMe storage, edge computing and automotive compute. |
| PCIe 5.0 | 32 GT/s per lane; current high-performance server and accelerator interconnect. | The principal near-term growth segment. AI servers and high-performance storage use Gen5 x16 links and switches to fan out high-bandwidth devices. |
| PCIe 6.0 | 64 GT/s, PAM4 signaling, FEC and Flit mode; up to 256 GB/s bidirectional on x16. | Early commercialization. Broadcom announced an end-to-end Gen6 portfolio for AI infrastructure, and Microchip has introduced Gen6 switch products for data-center designs. |
Architecture and lane configuration
The source scope also separates root-port, switch-port and multi-host architectures and lane configurations from x1/x4 through x32 and above. Switch-port designs form the core discrete market because they fan one upstream connection into multiple downstream endpoints. Multi-host switching is strategically important in composable systems because it allows multiple CPUs to access shared peripherals or memory resources. High-lane-count devices command the greatest value in AI and storage systems, where port count, non-blocking bandwidth and telemetry matter more than minimum package cost.
Segment Analysis: By Application
By application, the market is segmented into server, SSD and other uses. SSD is the largest application in the source scope, while AI and high-performance servers are the strongest value-growth area because a single system can contain multiple GPUs, NICs, NVMe devices and accelerators that compete for CPU-attached lanes.
| Application | Demand characteristics |
|---|---|
| Server | AI, HPC and cloud servers use switches to increase endpoint fanout, balance devices across CPU sockets and support peer-to-peer traffic. The move to Gen5 and Gen6 raises switch ASPs and design complexity. |
| SSD | Storage arrays and JBOFs use PCIe switches to aggregate many NVMe drives behind one or more hosts. Port count, latency, hot-plug, non-transparent bridging and failover features determine supplier selection. |
| Other | Networking, telecommunications, automotive, industrial and edge systems use lower-lane-count or ruggedized switches where lifecycle support, temperature range and deterministic behavior matter more than maximum bandwidth. |
Regional Analysis
China is the largest country market in the published dataset, supported by server manufacturing, storage production and a large domestic electronics ecosystem. North America is the leading innovation and early-adoption center for hyperscale AI architectures, while Asia Pacific overall has the broadest electronics manufacturing base and is the fastest-growing regional demand pool.
How does regional demand differ across the PCIe switch chips market?
Regional demand follows system design and data-center deployment more closely than semiconductor fabrication alone. North America creates many first-wave design wins because hyperscalers, AI platform companies and server OEMs define leading architectures there. China combines large server and electronics manufacturing volume with domestic cloud and AI investment. Taiwan is critical through server ODM and motherboard production. Europe has a smaller volume base but strong automotive, industrial and HPC demand, while South America and the Middle East & Africa are more closely tied to data-center buildout and imported server platforms.
| Region | Position | Growth outlook | Demand profile | What decides supplier selection |
|---|---|---|---|---|
| Asia Pacific | Largest manufacturing base | Fast | Server ODM, storage, cloud and electronics production | Cost, ecosystem support, lane density, qualification and supply continuity |
| North America | Innovation / early adoption hub | Strong | Hyperscale AI, cloud, enterprise storage and server architecture | Gen5/Gen6 roadmap, interoperability, software, telemetry and power |
| Europe | Specialized | Moderate | Automotive, industrial, HPC and sovereign cloud | Reliability, lifecycle, functional safety and long-term supply |
| South America | Small | Selective | Cloud regions, telecom and enterprise IT | Availability, system-OEM qualification and import economics |
| Middle East & Africa | Emerging | Project-led | AI data centers, cloud regions and smart-city infrastructure | Deployment support, system availability and hyperscaler ecosystem |
Key PCIe Switch Chips Manufacturers and Competitive Landscape
The PCIe switch-chip market is concentrated because high-speed SerDes design, protocol compliance, firmware, interoperability and customer qualification require sustained investment. Broadcom and Microchip are the clearest dedicated switch leaders in contemporary data-center platforms, while Texas Instruments, ASMedia, Diodes and other semiconductor companies address selected switch, bridge or connectivity niches.
Competition increasingly depends on complete platform capability rather than the switch die alone. Hyperscale customers evaluate lane count, port flexibility, latency, power, telemetry, error containment, hot-plug behavior, multi-host support, firmware tooling and interoperability with CPUs, GPUs, NICs, SSDs and retimers. The vendor that reduces system-validation time can win even at a higher chip price because delayed server qualification is much more expensive than the component delta.
Broadcom is pushing the top end of the market with Gen6 switch and retimer products aimed at AI infrastructure. Microchip competes with Switchtec families spanning storage, data center, embedded and automotive use cases and has highlighted strong growth in its dedicated data-center solutions business. Other suppliers compete more selectively through cost, lower-lane-count devices, embedded features, automotive qualification or adjacent bridge functions.
The technology roadmap raises barriers further. PCIe 6.0’s PAM4 signaling, FEC and Flit mode require new PHY and protocol implementation, while PCIe 7.0 doubles the raw rate again to 128 GT/s. Each generation therefore increases the value of proven SerDes IP, packaging expertise, compliance infrastructure and ecosystem relationships.
Tier structure
| Competitive tier | Representative companies | Strategic position |
|---|---|---|
| Tier 1 – data-center switch leaders | Broadcom; Microchip Technology | High-lane-count Gen5/Gen6 portfolios, deep server/storage ecosystem relationships, advanced telemetry and multi-host features. |
| Tier 2 – diversified connectivity suppliers | Texas Instruments; ASMedia Technology; Diodes Incorporated; NXP Semiconductors; Renesas Electronics | Compete in selected switch, bridge, embedded, automotive and lower-port-count applications. |
| Tier 3 – adjacent / specialist participants | Intel; AMD; Marvell; MaxLinear; Spectra7; Microsemi legacy products | Participate through platform integration, adjacent connectivity IP, legacy portfolios or specialized high-speed products. |
Key companies profiled
Broadcom; Microchip Technology Inc.; Texas Instruments; ASMedia Technology Inc.; Diodes Incorporated; NXP Semiconductors; Intel Corporation; AMD; Marvell Technology; Microsemi (part of Microchip); Renesas Electronics; MaxLinear; and Spectra7.
PCIe Switch Chips Production Capacity Analysis
For PCIe switch chips, the practical supply constraint is not a dedicated switch-chip fab. Most leading vendors are fabless or rely on external foundry capacity, advanced packaging and high-speed test capability. Effective production capacity is therefore a combination of wafer allocation on suitable process nodes, SerDes-qualified silicon, package substrate availability, high-speed ATE capacity and firmware readiness.
Gen5 and Gen6 devices raise silicon complexity and I/O density, pushing vendors toward advanced process nodes and higher-end packaging. Large reticle-area dies and high lane counts can reduce die-per-wafer economics, while package escape and board routing become more challenging. Because hyperscale programs often require high volume once qualified, suppliers need reserved foundry and test capacity before the customer ramp begins.
The market is also exposed to concentration risk in foundry and packaging ecosystems. A switch vendor can hold strong IP yet still face shipment constraints if substrate, test socket or advanced-node wafer capacity is tight. For customers, multi-sourcing is difficult because switch firmware and topology behavior can be platform-specific, so supply assurance becomes part of the design-in decision.
PCIe Switch Chips Market Dynamics: Drivers, Restraints and Opportunities
PCIe switch demand is being pulled upward by AI-server endpoint density, NVMe storage expansion and the transition to Gen5 and Gen6, while design complexity, power and long qualification cycles restrain supply. CXL creates the largest architectural opportunity because it extends PCIe-based switching into coherent memory and composable resource fabrics.
MARKET DRIVERS
Drivers Impact Analysis*
| Factor | Direction | What drives demand |
|---|---|---|
| United States | Primary market | Hyperscale cloud, AI infrastructure, enterprise storage and semiconductor vendors create the region’s core demand. |
| Canada | Cloud / AI expansion | Data-center growth and AI research support imported high-performance server platforms. |
| Mexico | Manufacturing-linked | Electronics and server assembly can create demand through North American supply chains. |
Full report coverage includes additional country-level revenue, sales and forecast detail within the defined regional scope.
Key PCIe Switch Chips Manufacturers and Competitive Landscape
The PCIe switch-chip market is concentrated because high-speed SerDes design, protocol compliance, firmware, interoperability and customer qualification require sustained investment. Broadcom and Microchip are the clearest dedicated switch leaders in contemporary data-center platforms, while Texas Instruments, ASMedia, Diodes and other semiconductor companies address selected switch, bridge or connectivity niches.
Competition increasingly depends on complete platform capability rather than the switch die alone. Hyperscale customers evaluate lane count, port flexibility, latency, power, telemetry, error containment, hot-plug behavior, multi-host support, firmware tooling and interoperability with CPUs, GPUs, NICs, SSDs and retimers. The vendor that reduces system-validation time can win even at a higher chip price because delayed server qualification is much more expensive than the component delta.
Broadcom is pushing the top end of the market with Gen6 switch and retimer products aimed at AI infrastructure. Microchip competes with Switchtec families spanning storage, data center, embedded and automotive use cases and has highlighted strong growth in its dedicated data-center solutions business. Other suppliers compete more selectively through cost, lower-lane-count devices, embedded features, automotive qualification or adjacent bridge functions.
The technology roadmap raises barriers further. PCIe 6.0’s PAM4 signaling, FEC and Flit mode require new PHY and protocol implementation, while PCIe 7.0 doubles the raw rate again to 128 GT/s. Each generation therefore increases the value of proven SerDes IP, packaging expertise, compliance infrastructure and ecosystem relationships.
Tier structure
| Competitive tier | Representative companies | Strategic position |
|---|---|---|
| Tier 1 – data-center switch leaders | Broadcom; Microchip Technology | High-lane-count Gen5/Gen6 portfolios, deep server/storage ecosystem relationships, advanced telemetry and multi-host features. |
| Tier 2 – diversified connectivity suppliers | Texas Instruments; ASMedia Technology; Diodes Incorporated; NXP Semiconductors; Renesas Electronics | Compete in selected switch, bridge, embedded, automotive and lower-port-count applications. |
| Tier 3 – adjacent / specialist participants | Intel; AMD; Marvell; MaxLinear; Spectra7; Microsemi legacy products | Participate through platform integration, adjacent connectivity IP, legacy portfolios or specialized high-speed products. |
Key companies profiled
Broadcom; Microchip Technology Inc.; Texas Instruments; ASMedia Technology Inc.; Diodes Incorporated; NXP Semiconductors; Intel Corporation; AMD; Marvell Technology; Microsemi (part of Microchip); Renesas Electronics; MaxLinear; and Spectra7.
PCIe Switch Chips Production Capacity Analysis
For PCIe switch chips, the practical supply constraint is not a dedicated switch-chip fab. Most leading vendors are fabless or rely on external foundry capacity, advanced packaging and high-speed test capability. Effective production capacity is therefore a combination of wafer allocation on suitable process nodes, SerDes-qualified silicon, package substrate availability, high-speed ATE capacity and firmware readiness.
Gen5 and Gen6 devices raise silicon complexity and I/O density, pushing vendors toward advanced process nodes and higher-end packaging. Large reticle-area dies and high lane counts can reduce die-per-wafer economics, while package escape and board routing become more challenging. Because hyperscale programs often require high volume once qualified, suppliers need reserved foundry and test capacity before the customer ramp begins.
The market is also exposed to concentration risk in foundry and packaging ecosystems. A switch vendor can hold strong IP yet still face shipment constraints if substrate, test socket or advanced-node wafer capacity is tight. For customers, multi-sourcing is difficult because switch firmware and topology behavior can be platform-specific, so supply assurance becomes part of the design-in decision.
PCIe Switch Chips Market Dynamics: Drivers, Restraints and Opportunities
PCIe switch demand is being pulled upward by AI-server endpoint density, NVMe storage expansion and the transition to Gen5 and Gen6, while design complexity, power and long qualification cycles restrain supply. CXL creates the largest architectural opportunity because it extends PCIe-based switching into coherent memory and composable resource fabrics.
MARKET DRIVERS
Drivers Impact Analysis*
| Factor | Direction | Relative impact on market growth |
|---|---|---|
| AI servers and accelerator fanout | Positive | High |
| NVMe storage and JBOF architectures | Positive | High |
| PCIe generation transition | Positive | High |
| Composable infrastructure and CXL | Positive | Medium-high |
AI servers multiply high-bandwidth endpoints
Modern AI systems connect multiple GPUs, NICs, DPUs and NVMe devices under one or more CPUs. NVIDIA’s reference architecture explicitly uses Gen5 x16 links and PCIe switches when additional fanout is required. As GPU count and peripheral density rise, direct CPU attachment becomes insufficient and switch silicon becomes a structural part of the server topology.
NVMe storage requires scalable fanout
PCIe switches allow a host or pair of hosts to connect to large numbers of NVMe drives while maintaining hot-plug, peer-to-peer traffic and failover behavior. This is critical in all-flash arrays, JBOFs and storage appliances, where a single high-lane-count switch can replace a much more complex set of direct links.
Gen5 and Gen6 raise value per design
Each PCIe generation doubles raw bandwidth. PCIe 6.0 reaches 64 GT/s and up to 256 GB/s bidirectional on x16, while PCIe 7.0 reaches 128 GT/s. Higher rates increase the technical value of the switch, retimer and compliance stack and support higher ASPs where customers need high lane density and validated interoperability.
CXL broadens the switching role
CXL uses the PCIe physical layer to support coherent memory and device connectivity. As CXL memory expansion and pooling move into production, switch architectures can support shared memory, composable resources and multi-host systems. This moves the addressable role from I/O expansion toward data-center resource orchestration.
MARKET RESTRAINTS
Restraints Impact Analysis*
| Factor | Direction | Relative impact on market growth |
|---|---|---|
| Signal-integrity and PHY complexity | Negative | High |
| Power and thermal limits | Negative | High |
| Lengthy OEM / hyperscaler qualification | Negative | Medium-high |
| Concentrated supplier base and platform lock-in | Negative | Medium |
PAM4 and higher frequencies complicate system design
PCIe 6.0 introduces PAM4 signaling, FEC and Flit mode to reach 64 GT/s. This raises channel-loss sensitivity and demands tighter equalization, package, connector and PCB design. Switch vendors must prove interoperability across a wide range of endpoints and retimers, increasing validation time and engineering cost.
Power limits lane density
A high-port-count switch sits in a thermally dense server next to CPUs, GPUs, SSDs and NICs. Higher lane rates increase SerDes power, so vendors must balance port count, reach and telemetry against rack-level power budgets. A design with excellent raw bandwidth can still lose if it forces more cooling or reduces system density.
Qualification slows adoption
Server OEMs and hyperscalers qualify switch silicon together with firmware, BIOS, retimers, endpoints and management software. A platform failure can affect an entire server fleet, so qualification is deliberate and conservative. This creates sticky design wins for incumbents and lengthens the revenue ramp for new suppliers.
MARKET OPPORTUNITIES
PCIe Gen6 AI infrastructure
Broadcom and Microchip are bringing Gen6 switch products into AI and data-center designs. Early deployments reward suppliers with mature compliance, telemetry and interoperability capabilities.
CXL memory switching and pooling
CXL 3.2 expands monitoring, security and memory-device functionality. As coherent memory expands, switch and fabric components can address workloads that need pooled or tiered memory beyond conventional PCIe endpoint fanout.
Automotive central compute
Domain controllers increasingly connect accelerators, networking devices and storage over PCIe. Automotive-qualified Gen4 and later switches create a growth path outside data centers, especially where redundancy and long lifecycle matter.
Edge and telecom systems
5G infrastructure, edge AI and industrial compute need compact switches with lower lane counts, deterministic performance and extended-temperature support, giving diversified suppliers a route to compete without matching hyperscale lane density.
PCIe Switch Chips Supply Chain Analysis
IP and architecture
Wafer fabrication
Packaging and test
System integration
The highest value capture sits in architecture, SerDes IP, firmware and validated ecosystem compatibility. Foundry manufacturing is essential but does not by itself create a competitive switch product. Suppliers differentiate through lane density, latency, error handling, multi-host behavior, telemetry and the software needed to configure and diagnose large fabrics.
Packaging and test become more critical as data rates increase. A Gen6 switch must preserve signal quality across package escape, PCB traces, connectors and sometimes retimers. Compliance testing therefore links semiconductor design directly to board and system engineering. Vendors with broad interoperability labs can shorten customer qualification and reduce deployment risk.
At the system level, OEM design-ins are sticky because topology, firmware and management behavior are integrated into the platform. This makes distribution less important than direct technical engagement for high-end switches. In lower-lane-count embedded and industrial products, broadline distribution and long lifecycle support play a larger role.
Recent Developments in the PCIe Switch Chips Market
| Date | Development | Market implication |
|---|---|---|
| June 2025 | PCI-SIG released PCIe 7.0 Version 1.0 at 128 GT/s. | Extends the roadmap beyond Gen6 and reinforces a three-year bandwidth-doubling cadence that drives continuing switch redesign. |
| February 2025 | Broadcom announced availability of an end-to-end PCIe Gen6 portfolio for AI infrastructure. | Moves Gen6 switching from specification to early platform deployment and raises competitive pressure on high-end switch vendors. |
| January 2025 | Microchip introduced a 16-lane Switchtec Gen4 family for automotive and embedded computing. | Demonstrates the expansion of discrete PCIe switching beyond data centers into central compute, industrial and embedded applications. |
| December 2024 | CXL Consortium released the CXL 3.2 specification. | Improves memory-device management, security and interoperability, supporting future switch opportunities in coherent memory fabrics. |
REPORT SCOPE & SEGMENTATION
| Attribute | Coverage |
|---|---|
| Market | PCIe Switch Chips |
| Base year | 2025 |
| Estimated year | 2026 |
| Forecast period | 2026–2034 |
| By type | PCIe 2.0; PCIe 3.0; PCIe 4.0; PCIe 5.0; PCIe 6.0 |
| By application | Server; SSD; Others |
| By end user | Cloud Service Providers; Enterprise Data Centers; Telecommunications; Others |
| By architecture | Root Port; Switch Port; Multi-Host |
| By lane configuration | x1/x4 Lanes; x8 Lanes; x16 Lanes; x32 Lanes & Above |
| Regions | North America; Europe; Asia Pacific; South America; Middle East & Africa |
| Companies profiled | Broadcom; Microchip Technology; Texas Instruments; ASMedia Technology; Diodes Incorporated; NXP Semiconductors; Intel; AMD; Marvell Technology; Microsemi; Renesas Electronics; MaxLinear; Spectra7 |
Frequently Asked Questions
What is the current size of the PCIe switch chips market?
The rebased market size is USD 938 million in 2025, rising to USD 1.04 billion in 2026 and USD 2.41 billion by 2034.
What CAGR is used for the 2026–2034 forecast?
The published 2024 and 2032 market-size anchors imply a compound annual growth rate of 11.1%, which is used for the rebased 2026–2034 series.
Which PCIe generation has the largest installed base?
PCIe 3.0 remains the largest installed-generation segment in the source scope, while growth is shifting toward PCIe 5.0 and PCIe 6.0.
Which applications use PCIe switch chips most heavily?
SSD and server platforms are the main applications because switches aggregate NVMe drives and expand connectivity for GPUs, NICs, DPUs and other accelerators.
Which market is the largest geographically?
China is the largest country market in the published dataset, while North America is the leading early-adoption and innovation hub for hyperscale AI architectures.
Why are PCIe switches important in AI servers?
AI servers contain many high-bandwidth endpoints but CPU lane counts are limited. PCIe switches create fanout and allow balanced connections among GPUs, network adapters and storage devices.
What changes in PCIe 6.0?
PCIe 6.0 reaches 64 GT/s and introduces PAM4 signaling, Forward Error Correction and Flit-mode encoding while maintaining backward compatibility.
How does CXL affect the PCIe switch market?
CXL uses the PCIe physical layer and expands the opportunity into coherent memory expansion, pooling and composable resource fabrics.
What are the main barriers to entry?
High-speed SerDes design, protocol compliance, firmware, interoperability testing, foundry access and lengthy OEM qualification create high barriers for new suppliers.
Which companies are profiled?
The profiled list includes Broadcom, Microchip, Texas Instruments, ASMedia, Diodes, NXP, Intel, AMD, Marvell, Microsemi, Renesas, MaxLinear and Spectra7.
Research Sources & Evidence Base
View research sources used for this overview
- PCI-SIG: PCI Express 6.0 Specification – PCIe 6.0 data rate, PAM4 signaling, FEC, Flit mode and backward compatibility.
- PCI-SIG: PCIe 7.0 Specification, Version 1.0 – Release timing and 128 GT/s roadmap for next-generation PCIe.
- PCI-SIG: PCI Express Base Specifications – Approved specification revisions through PCIe 7.0.
- CXL Consortium: CXL 3.2 Specification announcement – CXL memory-device management, security and coherent interconnect roadmap.
- Broadcom: Broadcom Extends PCIe Industry Leadership with End-to-End Gen 6 Portfolio for AI Infrastructure – PCIe Gen6 switch, retimer and interoperability platform for AI infrastructure.
- Microchip Technology: Switchtec PCIe Gen4 16-Lane Switches for Automotive and Embedded Computing – Automotive, industrial and embedded applications for PCIe switches.
- Microchip Technology: Data Center Solutions Business Unit Revenue Information – Data-center switch, retimer and controller portfolio growth including Gen6 PCIe.
- NVIDIA: AI Enterprise Reference Architecture – Compute Node Hardware – Use of Gen5 PCIe links and PCIe switches in GPU server reference architectures.
- NVIDIA: Enterprise Reference Architecture White Paper – Example 8-GPU server topology using PCIe Gen5 switches, GPUs, NICs and NVMe.
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