Key Statistics
Key Takeaways
- 2026 revenue: USD 3,573.62 million is the modeled value of original-generation HBM2 memory stacks, using the publisher’s 2024 and 2032 endpoints as the mathematical anchor; accelerator cards, servers, packaging services and HBM2E are outside the sales boundary. The 2026 estimate is a scenario rather than a disclosed manufacturer shipment total.
- Long-range outlook: USD 11,273.55 million in 2036 and a 12.2% annualized increase follow from endpoint extrapolation, but the result must be interpreted with caution because HBM2E, HBM3, HBM3E and HBM4 have replaced original HBM2 in many high-end designs. The projection is a revenue path, not a commitment by any memory producer.
- Capacity mix: Original 8 G stacks hold an estimated ~64% of modeled 2026 HBM2 revenue, while 4 G devices retain ~35% and other original configurations ~1%. The publisher’s 16 G category is retained for taxonomy continuity at ~0% original-HBM2 allocation, since the verified 16 GB products in the publisher narrative are HBM2E products.
- Applications: Servers represent an estimated ~62% of original-HBM2 revenue, supported by AMD Instinct MI100 and the archived Summit V100 installed base. Networking receives ~17%, consumer electronics ~7%, and specialist uses ~14% in the private model. These percentages represent mutually exclusive primary purchase applications rather than shipment disclosures.
- Geography: Asia-Pacific leads with a modeled ~48% of 2026 revenue, followed by North America at ~31%, Europe ~13%, South America ~4% and Middle East & Africa ~4%. The allocations are demand-attribution assumptions; South Korean supplier locations and US computing deployments support the qualitative ranking but do not establish audited country sales.
HBM2 DRAM Market Overview
HBM2 DRAM market was modeled at USD 3,573.62 million in 2026 and is projected at USD 11,273.55 million by 2036, equivalent to a 12.2% CAGR over the 2026–2036 endpoint window. The 2027 estimate is USD 4,008.70 million. This boundary covers factory-gate revenue for finished original-generation HBM2 DRAM stacks only; it excludes HBM2E, HBM3, HBM3E, HBM4, GPUs, integrated accelerator cards, servers, IP royalties and outsourced packaging services. Asia-Pacific is assigned an estimated ~48% share in the private allocation model, not a verified supplier revenue split.
HBM2 is a vertically stacked dynamic random-access memory architecture with an unusually wide interface, intended to keep processors supplied with data while reducing energy per transferred bit relative to narrow off-package links. Samsung described an 8 GB HBM2 stack using eight 8-gigabit memory dies and through-silicon vias in July 2017, then introduced Aquabolt in January 2018 at 2.4 gigabits per second per pin and 307.2 gigabytes per second per stack. These product disclosures establish real historical technology, not a continuously measured 2026 sales series.
A defining distinction is the memory generation. Samsung’s original 8 GB HBM2 Aquabolt should not be counted together with its later 16 GB Flashbolt HBM2E, which the manufacturer announced in February 2020. SK hynix separately announced HBM2E development in August 2019 and full-scale production in July 2020 at more than 460 gigabytes per second. Although both generations use vertically stacked DRAM, their specifications, product qualification cycles and customer replacement patterns differ materially, so combining them would double count a successor segment.
Original HBM2 reached substantial computing deployments. AMD lists its Instinct MI100 accelerator, launched on 16 November 2020, with 32 GB of HBM2, a 4,096-bit memory interface and 1.2 terabytes per second of board memory bandwidth. Oak Ridge National Laboratory’s archived Summit documentation describes roughly 4,600 compute nodes, each normally equipped with six NVIDIA V100 accelerators and 96 GB of HBM2. Summit was decommissioned in November 2024, demonstrating why an installed-base reference must not be mistaken for current-year merchant demand.
The growth arithmetic derives from the publisher’s US$2.84 billion 2024 headline and US$7.12 billion 2032 forecast. Their eight-year ratio implies roughly 12.17% compound growth, consistent with the published rounded growth label. Extending that ratio beyond 2032 yields a positive 2036 scenario, but the technology’s market life is contested by newer HBM generations. The model therefore separates mathematical consistency from commercial plausibility, especially when interpreting demand after large original-HBM2 computing platforms are retired.
The substitution timeline is observable in primary announcements. NVIDIA disclosed an 80 GB A100 using HBM2E in November 2020, SK hynix announced HBM3 supply in June 2022 and HBM3E volume production in March 2024, and Samsung disclosed commercial HBM4 shipments in February 2026. AMD’s MI300X platform specifies 1.5 TB of HBM3 across eight accelerators, while Micron’s current high-bandwidth memory portfolio highlights HBM3E and HBM4. These developments constrain the practical opportunity for new original-HBM2 design wins even as some older platforms continue operating.
Segment Analysis: By Type
The original publisher taxonomy is retained as 4 G, 8 G, 16 G and Others, but it is interpreted strictly by actual memory generation. The 8 G configuration is the leading verified original-HBM2 product, holding a modeled ~64% of 2026 sales, and the 4 G class is assigned ~35%. The 16 G category has ~0% original-HBM2 revenue because the publicly documented 16 GB stacks are HBM2E; keeping the row prevents an otherwise hidden scope change.
| Original HBM2 type | Product and evidence boundary | Modeled commercial position |
|---|---|---|
| 4 G | Four-gigabyte original-HBM2 stacks precede the later eight-gigabyte designs and suit qualified systems whose accelerator board layout and software remain unchanged. Samsung’s July 2017 announcement explicitly described its 8 GB product as having double the capacity of 4 GB HBM2, establishing the earlier configuration. The modeled category excludes any 4 GB GDDR memory or subsequent HBM generations and is tied to legacy platform qualification rather than broad new AI deployment. | An estimated ~35% of the 2026 original-HBM2 revenue pool is allocated to 4 G products, with a modeled ~10.7% ten-year growth path used solely to reconcile the published market endpoints. The share does not imply current manufacturing capacity or new-design momentum. Retained systems can generate repair, replacement and specialist procurement, while long-life installations may extend use beyond the commercial lifetime of their original GPU model. |
| 8 G | Samsung disclosed 8 GB HBM2 volume increases in July 2017 at 256 GB/s and launched Aquabolt in January 2018 at 307.2 GB/s. Eight 8-gigabit DRAM dies and thousands of TSV connections were used to obtain capacity without a conventional wide external board bus. These specific original-HBM2 disclosures make the eight-gigabyte tier the strongest independently supported type, distinct from 16 GB HBM2E and higher-generation devices. | The model assigns ~64% of original-HBM2 2026 revenue to 8 G stacks and a ~13.0% annual scenario growth rate, reflecting the product’s importance in established accelerator and HPC configurations. This modeled share is not a Samsung shipment disclosure. Demand may persist where replacing a qualified board requires a costly system redesign, but new HBM4-based platforms reduce the likelihood that original HBM2 remains a preferred option in leading-edge AI training. |
| 16 G | The publisher table of contents includes a 16 G category, yet the official 16 GB memory launches inspected for this review are Samsung Flashbolt and SK hynix HBM2E rather than original HBM2. Preserving a 16 G row without distinguishing the generation would transfer successor revenue into the wrong market. For this model, the category is shown for comparability but is not treated as an established merchant original-HBM2 configuration. | A ~0% share is assigned to 16 G original HBM2 in 2026, with no positive revenue attributed to the class across the model horizon. The zero reflects a conservative boundary decision, not proof that every possible engineering prototype was absent. If an original-HBM2 16 GB commercial product is documented later, the taxonomy can be revisited; until then, Flashbolt and 460 GB/s SK hynix HBM2E are counted outside this market. |
| Others | Other original-HBM2 configurations cover qualified custom or unusual capacities that are neither the documented 4 G nor the standard 8 G class, excluding memory modules that are explicitly HBM2E or later. This residual category should remain small because memory stacks are tightly qualified with processor packages and cannot be swapped like socketed server DIMMs. Specialist engineering demand is plausible, but manufacturer catalogs do not establish a large standalone merchant market for such variants. | The residual category receives a modeled ~1% of 2026 revenue and a ~4.0% annual scenario growth rate, yielding the endpoint reconciliation without forcing unverified product claims. Its share is deliberately modest and should not be read as proof of specific new chip launches. Procurement is likely to be bespoke, board-specific or repair-led, with documentation and support often more important than peak bandwidth or lower cost per gigabyte. |
Additional segmentation: bandwidth, workload and buyer channel
Beyond the original type taxonomy, the private model separates bandwidth below 200 GB/s, 200–300 GB/s and above 300 GB/s, with estimated 2026 shares of ~25%, ~46% and ~29%. The high-speed class is grounded technically by Samsung Aquabolt at 307.2 GB/s, but the revenue allocation is not supplied by Samsung. By workload, scientific HPC leads at ~42%, enterprise AI represents ~30%, professional graphics ~18% and specialist networking ~10%, with every sale assigned to one primary use.
The buyer-channel model allocates ~58% of 2026 stack revenue to accelerator and processor OEMs, ~29% to server and HPC integrators and ~13% to replacement or specialist buyers. These are distinct purchase pathways rather than extra revenues layered on top of the type model. In the forecast matrix below, each row shows a modeled annual USD-million allocation derived from its 2026 share and segment growth assumption. Totals across any single axis reproduce the same global market, so rows from different axes must never be summed together.
| Model axis / segment | 2026 | 2027 | 2028 | 2029 | 2030 | 2031 | 2032 | 2033 | 2034 | 2035 | 2036 |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Region: Asia-Pacific (~48% 2026) | 1,715.3 | 1,938.3 | 2,190.3 | 2,475.1 | 2,796.8 | 3,160.4 | 3,571.3 | 4,035.5 | 4,560.1 | 5,152.9 | 5,822.8 |
| Region: North America (~31% 2026) | 1,107.8 | 1,236.3 | 1,379.7 | 1,539.8 | 1,718.4 | 1,917.7 | 2,140.2 | 2,388.5 | 2,665.5 | 2,974.7 | 3,319.8 |
| Region: Europe (~13% 2026) | 464.6 | 512.9 | 566.2 | 625.1 | 690.1 | 761.9 | 841.1 | 928.6 | 1,025.2 | 1,131.8 | 1,249.5 |
| Region: South America (~4% 2026) | 142.9 | 156.8 | 172.0 | 188.7 | 207.0 | 227.1 | 249.1 | 273.3 | 299.8 | 328.9 | 360.8 |
| Region: Middle East & Africa (~4% 2026) | 142.9 | 162.7 | 185.1 | 210.7 | 239.7 | 272.8 | 310.4 | 353.3 | 402.0 | 457.5 | 520.6 |
| Type: 4 G (~35% 2026) | 1,250.8 | 1,384.6 | 1,532.8 | 1,696.8 | 1,878.3 | 2,079.3 | 2,301.8 | 2,548.1 | 2,820.7 | 3,122.5 | 3,456.6 |
| Type: 8 G (~64% 2026) | 2,287.1 | 2,584.4 | 2,920.4 | 3,300.1 | 3,729.1 | 4,213.9 | 4,761.7 | 5,380.7 | 6,080.2 | 6,870.6 | 7,763.8 |
| Type: 16 G (~0% 2026) | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 |
| Type: Others (~1% 2026) | 35.7 | 37.2 | 38.7 | 40.3 | 41.9 | 43.6 | 45.3 | 47.2 | 49.1 | 51.1 | 53.2 |
| Application: Servers (~62% 2026) | 2,215.6 | 2,505.9 | 2,834.2 | 3,205.4 | 3,625.4 | 4,100.3 | 4,637.4 | 5,244.9 | 5,932.0 | 6,709.1 | 7,588.0 |
| Application: Networking (~17% 2026) | 607.5 | 676.2 | 752.6 | 837.6 | 932.3 | 1,037.6 | 1,154.9 | 1,285.4 | 1,430.6 | 1,592.3 | 1,772.2 |
| Application: Consumer electronics (~7% 2026) | 250.2 | 271.9 | 295.6 | 321.3 | 349.2 | 379.6 | 412.7 | 448.6 | 487.6 | 530.0 | 576.1 |
| Application: Others (~14% 2026) | 500.3 | 552.0 | 609.0 | 671.9 | 741.4 | 818.0 | 902.5 | 995.7 | 1,098.6 | 1,212.1 | 1,337.3 |
| Bandwidth Class: Below 200 GB/s (~25% 2026) | 893.4 | 977.4 | 1,069.3 | 1,169.8 | 1,279.7 | 1,400.0 | 1,531.6 | 1,675.6 | 1,833.1 | 2,005.4 | 2,193.9 |
| Bandwidth Class: 200–300 GB/s (~46% 2026) | 1,643.9 | 1,839.5 | 2,058.4 | 2,303.3 | 2,577.4 | 2,884.1 | 3,227.4 | 3,611.4 | 4,041.2 | 4,522.1 | 5,060.2 |
| Bandwidth Class: Above 300 GB/s (~29% 2026) | 1,036.3 | 1,186.8 | 1,359.1 | 1,556.3 | 1,782.3 | 2,041.0 | 2,337.2 | 2,676.5 | 3,065.0 | 3,509.9 | 4,019.4 |
| End-Use Workload: Scientific HPC (~42% 2026) | 1,500.9 | 1,669.0 | 1,856.0 | 2,063.8 | 2,295.0 | 2,552.0 | 2,837.8 | 3,155.7 | 3,509.1 | 3,902.1 | 4,339.2 |
| End-Use Workload: Enterprise AI (~30% 2026) | 1,072.1 | 1,230.8 | 1,412.9 | 1,622.0 | 1,862.1 | 2,137.7 | 2,454.0 | 2,817.2 | 3,234.2 | 3,712.8 | 4,262.3 |
| End-Use Workload: Professional graphics (~18% 2026) | 643.3 | 708.2 | 779.8 | 858.5 | 945.2 | 1,040.7 | 1,145.8 | 1,261.5 | 1,388.9 | 1,529.2 | 1,683.7 |
| End-Use Workload: Networking and specialist (~10% 2026) | 357.4 | 395.6 | 438.0 | 484.9 | 536.8 | 594.3 | 658.0 | 728.4 | 806.4 | 892.8 | 988.4 |
| Buyer Channel: Accelerator and processor OEMs (~58% 2026) | 2,072.7 | 2,340.1 | 2,641.9 | 2,982.8 | 3,367.5 | 3,801.9 | 4,292.4 | 4,846.1 | 5,471.3 | 6,177.1 | 6,973.9 |
| Buyer Channel: Server and HPC integrators (~29% 2026) | 1,036.3 | 1,155.5 | 1,288.4 | 1,436.6 | 1,601.8 | 1,786.0 | 1,991.4 | 2,220.4 | 2,475.7 | 2,760.5 | 3,077.9 |
| Buyer Channel: Replacement and specialist buyers (~13% 2026) | 464.6 | 511.7 | 563.7 | 620.9 | 683.9 | 753.4 | 829.9 | 914.1 | 1,006.9 | 1,109.1 | 1,221.7 |
Segment Analysis: By Application
Application segmentation follows the original publisher labels Servers, Networking, Consumer electronics and Others. Servers lead with an estimated ~62% share in 2026, supported by the AMD Instinct MI100 and Oak Ridge Summit use cases. Networking is modeled at ~17%, consumer electronics ~7% and other specialist applications ~14%. These allocations describe the principal use of each memory stack and deliberately exclude the price of a completed server or accelerator card.
| Application | Demand characteristics |
|---|---|
| Servers | Servers are assigned an estimated ~62% of 2026 original-HBM2 revenue because the strongest documented installations are accelerator-equipped compute systems. AMD’s MI100 product specifies 32 GB HBM2 and 1.2 TB/s aggregate bandwidth, while the Summit archive records 96 GB HBM2 in a typical six-V100 node. The forecast assumes residual maintenance and qualified platform use, but newer HBM3 and HBM4 server designs make the long-range revenue trajectory highly sensitive to substitution. |
| Networking | Networking accounts for a modeled ~17% of 2026 original-HBM2 revenue, including high-throughput packet-processing or specialist compute equipment whose boards require wide, low-energy memory interfaces. Samsung’s 2017 8 GB HBM2 announcement listed network systems among potential applications, which supports the technical category without measuring shipments. The forecast reflects equipment refresh cycles and niche qualifications; conventional networking hardware still relies heavily on other memory technologies where HBM bandwidth is unnecessary. |
| Consumer electronics | Consumer electronics receives an estimated ~7% of 2026 original-HBM2 revenue, primarily reflecting historical premium graphics designs rather than mainstream phones, laptops or mass-market appliances. Samsung’s 2018 Aquabolt announcement explicitly included graphics systems among intended uses, but that statement does not establish broad consumer penetration. The category is constrained by cost, interposer integration and thermal design, so modeled demand should be interpreted as a narrow performance-oriented subset rather than a general electronics memory market. |
| Others | The modeled ~14% residual covers scientific instruments, research accelerators, industrial visualization and custom high-bandwidth platforms not cleanly assigned to the three named application classes. The Oak Ridge Summit documentation shows why long-lived scientific deployments can create specialist procurement requirements even after newer architectures enter the market. No specific revenue figure is attributed to an individual laboratory, and the scenario keeps replacement parts separate from sales of complete compute systems or service contracts. |
The end-use split should not be confused with the separate workload axis. A server may run artificial intelligence, scientific simulation or graphics workloads, but its original-HBM2 stack is counted once under Servers and once under the independent workload classification. The same discipline applies to bandwidth classes and buyer channels. In 2026, the model places ~42% of workloads in scientific HPC and ~30% in enterprise AI, while the application axis allocates ~62% to servers. These percentages answer different questions and are not additive.
New-platform announcements highlight the application boundary. NVIDIA’s November 2020 A100 80 GB launch explicitly used HBM2E, while AMD’s December 2023 MI300X platform specifies HBM3. Both products demonstrate the scale of demand for high-bandwidth memory in computing, but neither provides original-HBM2 stack revenue. The model therefore treats their specifications as substitution evidence rather than direct support for the projected 2036 HBM2 market size.
Regional Analysis
The private 2026 regional model assigns Asia-Pacific ~48% of original-HBM2 revenue, North America ~31%, Europe ~13%, South America ~4% and Middle East & Africa ~4%. These shares are modeled from supplier locations, historical computing platforms and application exposure; none is a published regional merchant-memory sales series. The geographic analysis distinguishes where memory is manufactured from where accelerator-equipped systems are purchased, preventing Asian supply from being counted twice as regional end demand.
Which regions account for modeled original-HBM2 DRAM revenue?
Asia-Pacific leads the modeled allocation because Samsung and SK hynix anchor the historical HBM production chain in South Korea and advanced semiconductor packaging is concentrated in Asian ecosystems. North America follows because AMD and NVIDIA platforms and Oak Ridge supercomputing facilities provide direct product evidence. The remaining regions are treated as downstream specialist markets rather than assumed manufacturers, and their shares reflect uncertainty about qualified installed systems rather than independently audited shipments.
| Region | Position | Growth outlook | Demand profile | What decides supplier selection |
|---|---|---|---|---|
| Asia-Pacific | Modeled ~48% 2026 share | Modeled ~13.0% CAGR | Installed qualified accelerators and HPC platforms | The original-HBM2 production story in Asia-Pacific is anchored by Samsung’s 2017 8 GB output expansion and 2018 Aquabolt launch. Processor qualification and advanced packaging determine which stacks can be integrated into a computing product. The later HBM2E and HBM4 announcements indicate a manufacturing shift, so a positive 2036 scenario must not be interpreted as proof of renewed old-generation capacity investment. |
| North America | Modeled ~31% 2026 share | Modeled ~11.6% CAGR | Installed qualified accelerators and HPC platforms | AMD’s MI100 accelerator and Oak Ridge Summit provide direct North American technology evidence, including 32 GB of board memory and 96 GB per typical Summit node. Those quantities describe installed systems rather than merchant stack revenue. Procurement outcomes depend on whether qualified machines survive, whether spare boards are obtainable and whether a newer accelerator offers a more economical lifecycle path. |
| Europe | Modeled ~13% 2026 share | Modeled ~10.4% CAGR | Installed qualified accelerators and HPC platforms | European demand is represented through potential scientific computing and industrial engineering workloads, not a claimed regional memory fab output figure. The original-HBM2 performance envelope can still matter where a specialized board remains qualified. However, global successor launches make new design adoption uncertain, and the regional scenario should be reconciled with installed hardware inventories before assigning any national sales estimate. |
| South America | Modeled ~4% 2026 share | Modeled ~9.7% CAGR | Installed qualified accelerators and HPC platforms | The South American model concerns imported specialist computing equipment and replacement economics, with no identified local merchant HBM2 stack factory in the reviewed evidence. Technical references such as Aquabolt describe capability but not Brazilian, Chilean or Argentine purchases. Maintenance compatibility, currency-sensitive equipment procurement and the retirement of older GPU platforms are the main conditional drivers of the regional scenario. |
| Middle East & Africa | Modeled ~4% 2026 share | Modeled ~13.8% CAGR | Installed qualified accelerators and HPC platforms | This modeled region is a potential end market for specialized imported accelerators, rather than a verified producer of original-generation stacked DRAM. AMD MI100 specifications establish a legacy component boundary, while Samsung HBM4 shows the performance available to new computing investments. The forecast is therefore sensitive to the balance between extending older qualified systems and adopting current memory technology in new projects. |
HBM2 DRAM Manufacturers and Competitive Landscape
Original HBM2 merchant supply is concentrated among specialized stacked-DRAM manufacturers, with Samsung’s 2017 and 2018 releases providing the clearest product-level evidence inspected for this market. SK hynix has deep HBM expertise but the cited later disclosures concern HBM2E and HBM3; Micron’s currently promoted products concern HBM3E and HBM4. Processor companies such as AMD and NVIDIA specify memory in accelerators but should not be mistaken for independent DRAM-stack manufacturers.
Samsung’s July 2017 release documented expanded 8 GB HBM2 output at 256 GB/s, followed by the January 2018 Aquabolt launch at 307.2 GB/s. Those announcements show that the competitive advantages of original HBM2 included TSV yield, thermal stability, stacking precision and qualification with demanding computing customers. They do not supply a 2026 vendor revenue split, and the private model does not convert Samsung’s historical production statement into a current market share.
SK hynix is an important HBM supplier across generations, yet its August 2019 development and July 2020 mass-production announcements specifically describe HBM2E at 16 GB and over 460 GB/s. SK hynix later disclosed HBM3 supply for NVIDIA in 2022 and HBM3E production in 2024. Those milestones are central to competition because they reduce the attractiveness of new original-HBM2 designs, even if the older generation remains installed in long-lived scientific and enterprise systems.
Micron’s current HBM portfolio prominently lists HBM3E and HBM4, which is evidence of successor competition rather than independently verified original-HBM2 production. AMD’s MI100 product and NVIDIA’s V100-equipped Summit platform document buyers of HBM2-equipped accelerators, while NVIDIA’s A100 80 GB and AMD’s MI300X illustrate transitions to HBM2E and HBM3. Competitive positioning therefore needs separate categories for DRAM manufacturers, accelerator integrators and historical end users.
Tier structure
| Tier | Companies | Basis of competition |
|---|---|---|
| Original-HBM2 product evidence | Samsung Electronics | Manufacturer with directly inspected 2017 8 GB HBM2 production expansion and 2018 Aquabolt mass-production disclosure. It is the strongest direct source for original-HBM2 capacity and bandwidth in this evidence set, although no audited 2026 revenue or market share is established. The position is generation-specific and should not be extended automatically to HBM2E or HBM4. |
| HBM ecosystem and successor supplier | SK hynix, Micron Technology | These manufacturers have significant HBM activity, but the official pages inspected here principally establish HBM2E, HBM3, HBM3E and HBM4. Their presence explains substitution and technology roadmaps, not a verified original-HBM2 2026 merchant sales allocation. A future supplier-level HBM2 ranking would require contract or shipment evidence that is not supplied by the current disclosures. |
| Processor and system ecosystem | AMD, NVIDIA, Oak Ridge National Laboratory | AMD MI100 and the Oak Ridge Summit V100 configuration establish actual original-HBM2 system use, while later AMD and NVIDIA platforms establish generation migration. These organizations influence memory qualification and demand but are not counted as merchant original-HBM2 DRAM producers. Their accelerator or system revenue must remain outside the memory-stack market boundary to avoid double counting. |
Key companies profiled
- Samsung Electronics
- SK hynix
- Micron Technology
- AMD
- NVIDIA
HBM2 DRAM Production and Capacity Analysis
Original HBM2 production depends on DRAM wafer fabrication, through-silicon-via formation, thinning, die stacking, bonding, testing and processor-package qualification. Samsung’s 2017 and 2018 disclosures show how thermal control and TSV design enabled higher bandwidth in commercial eight-gigabyte stacks. The production system is concentrated and capital-intensive, but current aggregate capacity for the original HBM2 generation cannot be inferred from company announcements about HBM2E, HBM3E or HBM4.
Samsung described more than 5,000 TSVs per die in its eight-high 8 GB HBM2 design and emphasized thermal bumps, clock-skew management and physical reinforcement when introducing Aquabolt. These details explain why yield and reliability are important supply-side determinants: a memory stack integrates multiple processed dies, so a packaging defect can affect the value of the entire assembled product. Higher qualified yield can reduce effective cost without any change in the headline interface speed.
The production landscape has evolved away from original HBM2. SK hynix’s 2020 HBM2E mass-production announcement reported 16 GB eight-high stacks with 460.8 GB/s throughput, and its March 2024 HBM3E release described improved heat dissipation and a new stacking process. Samsung’s February 2026 HBM4 announcement described a 4 nm logic base die and 2,048 data pins. These developments demonstrate shared expertise across generations, not evidence that old HBM2 capacity is still expanding at the same pace.
Supply for long-life original-HBM2 equipment is shaped by qualification, last-time-buy policies and the cost of redesigning an accelerator package. The Oak Ridge Summit archive records 96 GB HBM2 in standard nodes and also records the machine’s November 2024 retirement, illustrating that a large installed base can disappear on a defined system lifecycle. Procurement teams evaluating legacy memory should therefore distinguish inventory availability, repair demand and continuing production rather than assuming a published 2036 revenue path represents manufacturer capacity plans.
HBM2 DRAM Market Dynamics: Drivers, Restraints and Opportunities
Original-HBM2 revenue in this forecast is driven by historical platform qualifications, specialist HPC workloads, repair inventories and systems that cannot economically change memory generation. These forces face powerful restraints from HBM2E, HBM3, HBM3E and HBM4 substitution, high packaging cost, supplier concentration and aging system fleets. The contribution model is a scenario decomposition whose signed entries reconcile arithmetically with the headline CAGR; they are not causal estimates verified by manufacturer sales.
MARKET DRIVERS
Drivers Impact Analysis
| Market Drivers | Impact Rank | CAGR Contribution (%) | 2027–2029 | 2030–2032 | 2033–2036 |
|---|---|---|---|---|---|
| Long-life qualified HPC and accelerator systems | High | +5.10% | High | Medium | Low |
| Specialist scientific and engineering workloads | High | +4.20% | High | Medium | Medium |
| Memory bandwidth requirements in legacy designs | Medium-High | +3.60% | Medium | High | Medium |
| Repair, spares and lifecycle extension | Medium | +2.80% | Medium | High | High |
| Compatibility cost of changing memory generation | Low-Medium | +2.00% | Medium | Medium | High |
| Others (small specialist integrations and maintenance contracts) | Low | +1.30% | Low | Medium | Low |
Qualified systems support replacement demand
AMD’s MI100 product documents 32 GB of original HBM2 on a 2020 accelerator, while Oak Ridge Summit used 96 GB HBM2 per standard compute node. Such systems demonstrate how memory is qualified as part of a tightly integrated processor package rather than as a socketed commodity module. For installations that remain operational, board compatibility can support specialist replacement procurement even when the broader technology ecosystem has moved to newer generations.
Scientific computing retains high-bandwidth requirements
The Summit archive illustrates scientific applications that need very high memory throughput and large parallel GPU fleets, and Samsung’s 2017 product release explicitly identified HPC among original-HBM2 targets. Some scientific users preserve validated workflows for years because changing hardware can require software and numerical requalification. The model therefore assigns a ~42% workload share to scientific HPC, while recognizing that a retired machine no longer generates new merchant memory demand.
Original HBM2 offers known performance envelopes
Samsung’s 8 GB HBM2 product progressed from 256 GB/s in 2017 to 307.2 GB/s Aquabolt in 2018, demonstrating a meaningful performance improvement inside the same broad generation. Established hardware specifications can reduce design uncertainty for specialist products that do not need HBM4-class bandwidth. The modeled ~29% share for above-300-GB/s HBM2 reflects this technical distinction, not a supplier-reported 2026 shipment mix.
Maintenance inventories extend technology lifecycles
A specialized accelerator is often embedded in a complete scientific instrument, server board or control environment with long software support obligations. When the processor and memory are packaged together, replacing a failed assembly can be simpler than qualifying a new compute architecture. This creates an economic rationale for legacy stock and maintenance contracts, though such spending must be attributed to the memory stack alone and not to complete replacement servers.
Interface qualification can outweigh peak bandwidth
HBM2 memory requires close physical integration with a processor and precise power, thermal and signal-integrity design. A move from HBM2 to HBM3 or HBM4 can require new packaging, controller and software validation rather than a simple memory swap. The model treats this friction as a support factor for residual demand, especially where system owners value proven operation over the absolute fastest data-transfer specification available in 2026.
MARKET RESTRAINTS
Restraints Impact Analysis
| Market Restraints | Impact Rank | CAGR Contribution (%) | 2027–2029 | 2030–2032 | 2033–2036 |
|---|---|---|---|---|---|
| HBM2E, HBM3E and HBM4 technology substitution | High | -3.10% | High | High | High |
| Aging installed systems and decommissioning | Medium-High | -1.80% | Medium | High | High |
| High stacked-DRAM packaging and qualification cost | Medium | -1.10% | High | Medium | Medium |
| Others (supplier concentration and support discontinuity) | Low | -0.80% | Medium | Medium | High |
New HBM generations displace original stacks
NVIDIA’s A100 80 GB release specified HBM2E in 2020, SK hynix announced HBM3 supply in 2022 and HBM3E volume production in 2024, and Samsung disclosed commercial HBM4 shipments in February 2026. These primary milestones establish that the leading performance segment has progressed well beyond original HBM2. A straight-line 2036 revenue extrapolation therefore faces substantial technology risk and should not be mistaken for a supplier capacity commitment.
Retirement removes qualified installed demand
Oak Ridge’s archived Summit documentation states that the system was decommissioned on 15 November 2024. The same archive records a large original-HBM2 fleet in its NVIDIA V100 nodes, showing that even a substantial deployment can cease operation within a forecast horizon. When such fleets retire, replacement demand can fall sharply despite rising total AI spending elsewhere, making platform survival a more important indicator than broad data-center capital expenditure.
Stacked memory remains costly to qualify
Samsung’s original HBM2 Aquabolt used thousands of through-silicon vias per die and specialized thermal features, increasing the process complexity compared with ordinary board-level DRAM. Packaging yield, interposer compatibility, thermal testing and long-term reliability requirements can keep prices elevated for low-volume legacy procurement. These technical barriers can restrain adoption in networking and consumer applications that obtain sufficient bandwidth from less complex memory architectures.
Supplier focus shifts toward current-generation products
Micron’s public HBM portfolio now highlights HBM3E and HBM4, and SK hynix and Samsung have issued numerous successor-generation announcements since 2020. That portfolio direction creates a support risk for buyers seeking original HBM2 late in the forecast period. Qualification documents, inventory visibility and contract terms may become more decisive than advertised throughput, particularly when customers require guaranteed supply for specialist equipment after mainstream accelerator designs have moved on.
MARKET OPPORTUNITIES
Lifecycle procurement for qualified HPC fleets
Research institutions and industrial operators with stable software workloads can prefer a compatible replacement accelerator over a costly full-platform upgrade. The AMD MI100 and Summit V100 configurations illustrate why original-HBM2 hardware is tied to particular system designs. Suppliers that can document provenance, reliability and thermal compatibility may capture specialist maintenance orders, although this opportunity is constrained by system retirements and must not be generalized into new high-volume AI memory demand.
Legacy professional graphics and visualization
Samsung’s 2018 Aquabolt announcement listed advanced graphics among original-HBM2 target applications, and its 2017 release included graphics alongside AI, HPC and network systems. This supports a niche opportunity in installed professional workstations or visualization appliances where bandwidth requirements remain fixed. Revenue prospects depend on repair inventory and long-term board support, not on a claim that contemporary consumer graphics designs are migrating back from newer memory technologies.
Technical support for integration and validation
The complexity of TSV stacking, thermal management and wide-interface integration can create demand for testing, reliability evaluation and memory subsystem engineering around older platforms. Those activities can improve customer retention for memory suppliers, but their service revenue is excluded from the factory-gate HBM2 stack boundary. The opportunity is therefore indirect: better qualification support can help sell or preserve stack contracts without expanding the market definition to consulting or packaging services.
Selective international specialist procurement
The modeled regional allocation places ~48% in Asia-Pacific and ~31% in North America, while smaller regions may buy original-HBM2-equipped equipment for specialized workloads. Importing a qualified accelerator does not mean a country has local HBM2 manufacturing, and a platform’s full sales value is not a memory-stack sale. The most credible opportunity is targeted procurement of compatible parts where system economics justify extending a proven installation rather than adopting an entirely new compute architecture.
HBM2 DRAM Supply Chain Analysis
The original-HBM2 supply chain begins with DRAM wafers and TSV processing, passes through stacking and thermal qualification, and ends when finished memory stacks are integrated with a processor package. Samsung’s documented 8 GB HBM2 architecture and AMD’s 32 GB MI100 accelerator illustrate the distinction between component production and end-system integration. The modeled revenue boundary stops at the memory stack, preventing double counting of interposers, GPUs, accelerator boards, server chassis and software.
Upstream wafer fabrication. High-bandwidth memory uses specialized DRAM dies whose TSV structures connect many layers vertically. Samsung’s 2017 disclosure described more than 5,000 TSVs per die and over 40,000 per 8 GB HBM2 package, providing a concrete example of the fabrication complexity. Wafer yield and known-good-die testing affect the economics of the complete stack, because a defective layer can compromise an otherwise valuable assembled memory product.
Stack assembly and reliability. Samsung’s Aquabolt release discussed extra thermal bumps, improved TSV timing and a protective lower layer to increase physical strength. These engineering details matter because stacked DRAM operates close to a high-power processor and has limited room for conventional cooling. Qualification must address sustained memory traffic, temperature cycling and interface reliability, so a mature original-HBM2 design may remain attractive for a stable platform even when faster successor stacks are available.
Integration and buyer qualification. AMD’s MI100 combines 32 GB HBM2 with a 4,096-bit interface and 1.2 TB/s memory bandwidth at the accelerator level, while Summit nodes used six V100 GPUs and 96 GB HBM2. These figures refer to finished compute systems, not individual stack sales. A memory supplier typically depends on the accelerator designer’s package qualification, which makes changes to memory generation more difficult than substituting a socketed DRAM module.
Downstream lifecycle and substitution. The transition from NVIDIA A100 HBM2E to AMD MI300X HBM3 and commercial Samsung HBM4 shows how fast the downstream performance frontier has moved. Customers maintaining original-HBM2 platforms face a different purchasing problem from buyers of new AI training clusters: they seek compatible replacements and reliable documentation. The long-range model therefore represents a mathematically extended revenue scenario rather than a manufacturer-backed forecast of original-generation memory production.
Recent Developments Affecting Original HBM2 DRAM
- 18 July 2017 Production
Samsung announced expanded production of 8 GB original HBM2 with 256 GB/s bandwidth and an eight-die TSV stack. The release identified AI, scientific computing, advanced graphics, network systems and enterprise servers as target uses. This is direct evidence of commercial original-HBM2 supply, but it does not quantify 2026 sales or validate any modeled regional share. Source - 11 January 2018 Launched
Samsung began mass-producing 8 GB Aquabolt HBM2 at 2.4 Gb/s per pin and 307.2 GB/s per stack, with enhanced TSV timing and thermal features. The specification marks an original-HBM2 product milestone and is used to define the high-bandwidth category without importing later 16 GB HBM2E specifications into the same market. Source - 4 February 2020 Successor
Samsung introduced 16 GB Flashbolt HBM2E for high-performance computing, moving beyond the capacity and bandwidth of Aquabolt. The development is relevant as substitution pressure rather than direct original-HBM2 growth. Its 16 GB configuration must remain outside the modeled original-HBM2 type category despite inconsistent descriptions in the publisher narrative. Source - 2 July 2020 Successor
SK hynix announced full-scale HBM2E production at 16 GB capacity and over 460 GB/s bandwidth, using eight stacked 16-gigabit dies. The launch indicates a transition in merchant high-bandwidth memory supply, reducing the expected attractiveness of new original-HBM2 designs while leaving some qualified older systems in operation. Source - 16 November 2020 Platform
AMD lists the Instinct MI100 launch on this date, with 32 GB HBM2, a 4,096-bit interface and 1.2 TB/s peak memory bandwidth. This provides direct original-HBM2 accelerator evidence, although the memory value is only a component of the finished GPU card and cannot be inferred from the accelerator selling price. Source - June 2022 Successor
SK hynix announced the supply of HBM3 DRAM to NVIDIA, establishing a newer generation in commercial accelerator procurement. The event matters to original-HBM2 forecasting because faster memory can win new high-performance designs. HBM3 units, pricing and revenue are excluded from the original-HBM2 boundary even when both technologies serve AI servers. Source - 19 March 2024 Successor
SK hynix began HBM3E volume production, reporting up to 1.18 TB/s throughput and improvements in heat dissipation. This official milestone further narrows the role of original HBM2 in leading-edge accelerator design. The projected 2036 original-HBM2 revenue should therefore be treated as a scenario rather than evidence of a continuing product-generation boom. Source - 12 February 2026 Successor
Samsung reported commercial shipments of HBM4 with 11.7 Gb/s pin speed and a 4 nm logic base die. This latest-generation milestone is a direct competitive threat to original HBM2 in new AI and HPC systems. The HBM4 stack value is excluded, and its existence is used to qualify the uncertainty surrounding the positive 2036 HBM2 extrapolation. Source
REPORT SCOPE & SEGMENTATION
| Attribute | Details |
|---|---|
| Study Period | 2024–2036 |
| Base Year | 2026 |
| Estimated Year | 2027 |
| Forecast Period | 2027–2036 |
| Historical Anchor | 2024 published headline |
| Market Size 2026 | USD 3,573.62 million |
| Market Size 2027 | USD 4,008.70 million |
| Market Size 2036 | USD 11,273.55 million |
| Growth Rate | CAGR of 12.2% from 2026–2036 |
| Measurement | Factory-gate value of finished original-HBM2 memory stacks; USD million |
| Revenue Exclusions | HBM2E, HBM3, HBM3E, HBM4, GPUs, complete servers, controller IP and packaging services |
| By Type | 4 G · 8 G · 16 G (taxonomy retained, zero original-HBM2 allocation) · Others |
| By Application | Servers · Networking · Consumer electronics · Others |
| By Bandwidth Class | Below 200 GB/s · 200–300 GB/s · Above 300 GB/s |
| By End-Use Workload | Scientific HPC · Enterprise AI · Professional graphics · Networking and specialist |
| By Buyer Channel | Accelerator and processor OEMs · Server and HPC integrators · Replacement and specialist buyers |
| By Region | Five-region analysis with modeled revenue allocation, distinct from manufacturer factory locations North AmericaUnited States · Canada · Mexico EuropeGermany · France · United Kingdom · Rest of Europe Asia-PacificSouth Korea · Taiwan · Japan · China · Rest of Asia-Pacific South AmericaBrazil · Chile · Argentina · Rest of South America Middle East & AfricaSaudi Arabia · UAE · South Africa · Rest of Middle East & Africa |
| Key Companies Profiled | Samsung Electronics; SK hynix; Micron Technology; AMD; NVIDIA. Manufacturer, platform integrator and ecosystem roles are distinguished in the competitive analysis. |
| Customization Scope | Optional country, platform and memory-generation reconciliation, original-HBM2 inventory and last-time-buy review, and separately scoped historical shipments for qualified computing systems. |
Frequently Asked Questions
What is the modeled size of the original HBM2 DRAM market in 2026?
The model values original-generation HBM2 memory stacks at USD 3,573.62 million in 2026, derived from the publisher’s 2024 and 2032 monetary endpoints. This is a mathematical scenario for memory-stack revenue, not a manufacturer-audited shipment total. It excludes HBM2E, HBM3, HBM3E, HBM4 and the selling price of GPUs or complete servers.
What is the forecast original HBM2 DRAM market size in 2036?
The 2036 scenario reaches USD 11,273.55 million after extending the publisher endpoint-implied annual growth rate. This result should not be interpreted as a commitment by Samsung or SK hynix to expand original-HBM2 output. The forecast is particularly exposed to substitution by HBM2E, HBM3E and HBM4, which already appear in official supplier announcements and modern accelerator platforms.
What annual growth rate does the model use?
The report applies a rounded 12.2% CAGR over the 2026–2036 window, consistent with the publisher’s 2024 US$2.84 billion and 2032 US$7.12 billion endpoints. The unrounded eight-year ratio implies about 12.17% annual growth. Segment rates vary and reconcile to the same aggregate forecast, but none is a verified supplier sales growth forecast.
Which HBM2 capacity type leads revenue?
The 8 G category leads with a modeled ~64% of 2026 original-HBM2 revenue, followed by 4 G at ~35% and Others at ~1%. Samsung’s official 2017 and 2018 releases directly support commercial 8 GB original HBM2. The 16 G row is retained from the publisher taxonomy but allocated ~0% because inspected 16 GB products are HBM2E, not original HBM2.
Which application contributes the largest modeled demand?
Servers represent an estimated ~62% of 2026 original-HBM2 stack revenue, with networking ~17%, consumer electronics ~7% and specialist uses ~14%. AMD’s Instinct MI100 and Oak Ridge Summit provide direct historical accelerator-system evidence. These shares classify the memory’s primary application and do not include the price of an entire server, GPU or maintenance service contract.
Which geographic region has the largest modeled share?
Asia-Pacific leads with an estimated ~48% of 2026 original-HBM2 revenue, followed by North America at ~31%, Europe ~13%, South America ~4% and Middle East & Africa ~4%. The allocation is based on South Korean memory supply and North American computing-platform evidence, not audited regional stack shipments. Country-level sales shares are not presented as verified observations.
How is original HBM2 different from HBM2E?
Original HBM2 includes Samsung’s 8 GB Aquabolt, specified at 307.2 GB/s per stack in January 2018. Samsung later introduced 16 GB Flashbolt HBM2E, while SK hynix disclosed 16 GB HBM2E above 460 GB/s in 2020. Those successor products have different capacities and performance envelopes, so combining them would inflate original-HBM2 revenue and misstate the generation boundary.
Are NVIDIA A100 and AMD MI300X counted as original HBM2 sales?
No. NVIDIA’s November 2020 A100 80 GB uses HBM2E, while AMD’s MI300X platform specifies HBM3. They are relevant because they document migration toward newer high-bandwidth memory generations, not because their accelerator sales validate the original-HBM2 market. Only finished original-HBM2 memory stacks are within the modeled factory-gate revenue boundary. In this market boundary, board-level capacity is evidence of the installed memory technology, never a substitute for factory-gate stack transaction values or independently reported component shipments.
How does the model treat Summit and other retired supercomputers?
The Oak Ridge Summit archive documents around 4,600 nodes with 96 GB HBM2 in a typical node and states that Summit was decommissioned on 15 November 2024. Its specifications demonstrate a real original-HBM2 installed platform, but retired equipment is not assumed to generate new 2026 memory orders. The long-range model must be evaluated against similar lifecycle retirements and replacement availability.
What is the principal uncertainty in the 2036 HBM2 forecast?
Technology substitution is the largest uncertainty. SK hynix announced HBM3 in 2022 and HBM3E volume production in 2024, while Samsung reported commercial HBM4 shipments in February 2026. These transitions could sharply reduce original-HBM2 new-design demand even as overall AI memory spending rises. The positive 2036 value is therefore a publisher-endpoint extension, not a verified manufacturer capacity or shipment plan.
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