Top 10 Leading NPU Companies Powering Next-Generation Artificial Intelligence and On-Device Processing

The Neural Processing Unit race in 2026 has shifted hard toward on-device intelligence, efficient inference, and specialized silicon that can run multi-billion-parameter models without constant cloud reliance.

Across smartphones, PCs, data centers, and edge systems, these ten players define how AI actually lands in real workloads from generative agents on phones to trillion-parameter serving clusters.

Nvidia continues to set the pace for high-volume AI acceleration even as dedicated NPU designs proliferate. Its data-center platforms, including the Vera Rubin generation succeeding Blackwell, deliver multi-petaflop-class performance across racks, with systems scaling to 144 GPUs per rack and optical links extending further.

• In fiscal 2026 the company posted record data-center revenue exceeding $193 billion, reflecting sustained demand for training and inference clusters.
• Recent moves such as the Groq licensing agreement expand its inference toolkit with SRAM-centric approaches, while edge modules like Jetson variants continue to ship hundreds of TOPS for robotics and autonomous systems.
• The software stack remains the practical glue that keeps developers locked in, even as pure-NPU alternatives target power-sensitive or cost-sensitive deployments.

Apple Inc. has doubled down on tightly integrated Neural Engine silicon that powers private, always-available AI across its device lineup. The A20 Pro, built on a 2 nm process and shipping in the iPhone 18 Pro series, features a dual 16-core Neural Engine configuration totaling 32 cores twice the AI processing capacity of the prior generation paired with a 50% jump in memory bandwidth. GPU-resident Neural Accelerators further accelerate FP8 math, enabling local large-language-model inference and generative features without constant network dependency.

On the Mac side, successive M-series chips maintain unified memory architectures that keep model weights close to the compute fabric, supporting multi-billion-parameter workloads with strong energy efficiency measured in the sub-picajoule-per-operation range for optimized kernels. This vertical integration turns every new device into a practical NPU endpoint for Apple Intelligence features.

Qualcomm is extending its Hexagon NPU architecture from mobile flagships into discrete and data-center inference silicon. The Snapdragon 8 Elite Gen 6 and Extreme variants, fabricated on 2 nm, incorporate a redesigned Hexagon NPU plus Sensing Hub that support mixture-of-experts models exceeding 30 billion parameters directly on-device. Discrete offerings such as the AI200 (shipping next year) and AI250 bring the same architecture to rack-scale systems, with configurations supporting up to 768 GB of memory per card and multi-chip racks functioning as unified computers.

In PCs, the Snapdragon X2 Elite line delivers 80 TOPS of NPU performance, while recent Dell Pro Max systems pair a discrete Qualcomm AI-100 Ultra NPU rated at 870 INT8 TOPS with up to 128 GB of memory to run local models containing as many as 120 billion parameters. The strategy positions Hexagon as a power-efficient alternative for inference-heavy agentic workloads.

Google treats its Tensor Processing Units as both internal infrastructure and a competitive inference platform. The seventh-generation Ironwood (TPU7x) delivers more than 4,600 teraflops of FP8 performance per chip with 192 GB of high-bandwidth memory, scaling into pods of 9,216 chips that share more than 1.7 petabytes of memory. Anthropic has secured access to as many as one million of these units, underscoring the scale already in deployment.

Newer eighth-generation designs split training-focused (8t) and inference-optimized (8i) variants, the latter expanding on-chip SRAM to keep key-value caches resident and reduce memory-wall bottlenecks. Third-party measurements have shown competitive tokens-per-dollar economics against leading GPU platforms on matched workloads, reinforcing Google’s push into efficient serving.

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MediaTek is pursuing always-on and generative AI through dual-NPU designs in its Dimensity flagship line. The Dimensity 9600 Pro, also on 2 nm, pairs a high-efficiency second-generation NPU that cuts power by roughly 40% for continuous sensing with a higher-performance NPU 1090 that improves large-language-model prefill by 51% and token generation per watt by 55%.

The architecture supports local models up to 30 billion parameters and ships alongside LPDDR6 memory and UFS 5.0 storage to ease bandwidth constraints that previously limited on-device generation. Devices using these chips are rolling out in the current quarter, targeting mid-to-high-end smartphones where sustained AI features such as real-time translation, agentic assistants, and camera intelligence must run efficiently under tight thermal and battery envelopes.

Samsung Electronics is advancing its Exynos NPU capabilities on the company’s own 2 nm GAA process. The Exynos 2600, positioned for Galaxy S26-series devices, delivers generative AI processing gains of up to 113% over the prior generation while incorporating Arm SME2 instructions for lower-latency machine-learning tasks on the CPU complex. Partnerships with optimization specialists enable larger models to run fully on-device through model compression that preserves accuracy.

Early production of the follow-on Exynos 2700 shows expanded die area dedicated to both GPU and NPU blocks, signaling continued prioritization of local AI performance for imaging, voice, and generative features across high-volume smartphone shipments.

Intel is recalibrating its accelerator portfolio around inference-friendly designs while maintaining client NPU presence. The GPU D-Series (formerly Crescent Island), now sampling to customers, offers up to 1.3 petaflops of FP8 compute, 1.5 TB/s of memory bandwidth, and configurations reaching 480 GB of LPDDR5X inside a 350-watt air-cooled PCIe card. A single card can host models up to roughly 300 billion parameters, with eight-GPU systems exceeding one trillion parameters.

On the client side, Core Ultra series 3 processors on Intel 18A deliver up to 50 NPU TOPS, meeting Copilot+ thresholds for local AI experiences. The dual track high-memory inference cards plus integrated NPUs targets both data-center serving economics and PC-based agentic workloads.

Huawei is scaling Ascend NPUs into massive multi-chip systems designed for domestic supply-chain resilience. The Ascend 950 series targets roughly one petaflop of FP8 and two petaflops of FP4 performance, with variants carrying 128-144 GB of custom high-bandwidth memory and bandwidths approaching 4 TB/s.

Larger SuperPoD configurations link as many as 8,192 chips into a single logical node delivering multi-exaflop FP4 throughput and hundreds of terabytes of unified memory, supported by proprietary high-speed interconnects that reduce hop latency into the hundreds of nanoseconds. Open-source kernel work from major model developers has already demonstrated near-peak sparse-attention throughput on these parts, illustrating growing software readiness for large-scale inference and training clusters.

Cambricon Technologies is ramping volume production of its Siyuan-series accelerators to meet domestic demand for Nvidia alternatives. Plans call for delivery of approximately half a million AI accelerators in 2026, including up to 300,000 units of the advanced Siyuan 590 and 690 models fabricated primarily on SMIC’s N+2 7 nm process.

Earlier MLU370-class cards already delivered 256 INT8 TOPS with 48 GB of memory in a 250-watt envelope; the newer 590-class parts raise the ceiling further with higher memory capacity and TOPS ratings. The focus remains inference-optimized silicon supplied to major cloud and internet platforms, with production targets representing more than a threefold increase over prior-year volumes.

Graphcore continues to refine its Intelligence Processing Unit architecture under SoftBank ownership, emphasizing high on-chip bandwidth and 3D stacking. The Bow IPU (Mk2x) employs wafer-on-wafer bonding of a deep-trench-capacitor die to the compute die, enabling roughly 40% higher clock rates or 20% lower power at equivalent performance.

Each chip integrates 1,472 tiles delivering hundreds of TFLOPS at FP16 with multi-terabyte-per-second on-chip bandwidth and tens of megabytes of SRAM. Next-generation Izanagi work combines the IPU fabric with Arm-based server CPUs for SoftBank’s large-scale infrastructure targets, preserving the architecture’s strength in sparse and irregular workloads while preparing for broader hyperscale deployment.