Ethernet Switch Chips Market 2026: 800G Deployments, 102.4T Silicon and the Road to 1.6T Networking

Ethernet switch chips are moving from conventional packet-forwarding components toward highly programmable silicon designed around AI clusters, cloud-scale computing and increasingly dense data-center fabrics. The change can be seen in the jump from 400G and 800G interfaces toward 1.6T Ethernet, alongside switch ASICs reaching 100 Tbps-class aggregate capacity.

• The Ethernet Alliance’s 2026 roadmap identifies 100G through 800G as active Ethernet speeds while placing 1.6Tb/s and higher technologies on the emerging roadmap for AI and cloud-scale infrastructure.
• The organization also highlights 2.5G, 5G and 10G Ethernet for enterprise, automotive and industrial applications.

A New Scale for Switching Silicon

The most visible change is the capacity being integrated into individual switch chips. Broadcom announced in March 2026 that its Tomahawk 6 family was shipping in production volume with 102.4 Tbps of switching capacity. Broadcom describes the chip as delivering twice the throughput of its previous Tomahawk generation and targeting both scale-up and scale-out AI networks.

Cisco reached the same 102.4 Tbps class with its Silicon One G300. The processor supports 64 × 1.6 Tbps Ethernet configurations and flexible port speeds spanning 10G, 25G, 40G, 50G, 100G, 200G, 400G, 800G and 1600G.

The progression can be viewed simply as:

400G Ethernet → 800G Ethernet → 1.6T Ethernet
↓
112G SerDes → 224G SerDes
↓
Higher port density + lower latency + greater switching capacity
↓
AI scale-out and scale-up networks

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Why 800G Is Becoming a Practical Design Point?

800G is no longer confined to technology demonstrations. NVIDIA’s Spectrum Ethernet portfolio includes switch platforms supporting up to 800 Gb/s, while its newer Spectrum-6 generation is designed around larger AI-networking requirements and co-packaged optics.

Cisco’s 2026 networking portfolio similarly includes 51.2T systems using Silicon One and 102.4T G300-based systems. The company’s G202, meanwhile, provides 25.6 Tbps and supports 64 × 400GE configurations for AI and web-scale leaf and top-of-rack applications.

This creates several practical switching tiers:

• 400G for established high-speed data-center fabrics
  • 800G for increasingly dense AI networking
  • 1.6T for next-generation high-bandwidth links
  • 3.2T and 6.4T as longer-term Ethernet roadmap targets

224G SerDes Opens the Door to 1.6T

The move toward 1.6T is not simply a matter of making a larger switch ASIC. Electrical signaling must also advance. Ethernet Alliance material identifies 224G signaling as a key technology for 1.6T connectivity, with the ecosystem working across switches, optics, cables and test equipment.

• In September 2026, the Ethernet Alliance announced a multi-vendor 1.6T interoperability demonstration at ECOC 2026 involving 224G SerDes, 1.6T OSFP connectivity and 800G lossless Ethernet demonstrations. The event brought together equipment, optics and testing participants to demonstrate how the pieces of the ecosystem operate together.

AI Is Changing What a Switch Chip Must Do

Traditional switching focused heavily on forwarding packets between endpoints. AI infrastructure introduces more demanding traffic patterns because thousands of accelerators can exchange enormous volumes of data during distributed training and inference.

The Ultra Ethernet Consortium’s 1.0.2 specification describes AI and HPC deployment models involving approximately 80,000 to 256,000 Ethernet ports, with target port speeds beginning at 800G for dedicated AI training environments. It also targets unloaded one-way latency of roughly 2 to 10 microseconds for these deployment models.

This is pushing switch silicon toward deeper traffic management, congestion control, telemetry, programmable processing and loss-aware networking.

Optical Integration Moves Closer to the Switch

Another important shift is the closer relationship between switching silicon and optics. Broadcom’s Tomahawk 6-Davisson platform combines 102.4 Tbps Ethernet switching with co-packaged optics, while Cisco is developing 1.6T and 800G optical connectivity around its high-capacity Silicon One platforms.

The architecture is increasingly becoming:

Switch ASIC → High-speed SerDes → Electrical/Optical Interface → 800G or 1.6T Link → AI Accelerator

Co-packaged optics and linear pluggable optics are particularly relevant because reducing electrical reach and optical-module power becomes increasingly important as bandwidth density rises.

Software Is Becoming Part of the Silicon Decision

Switch-chip selection is no longer purely a hardware specification exercise. Network operating systems and programmable interfaces increasingly influence how the silicon is deployed.

SONiC, the open-source network operating system hosted by the Linux Foundation, was created to allow cloud providers, operators and enterprises to customize networking environments. Its ecosystem is closely associated with switch abstraction through the Switch Abstraction Interface, creating a software layer that can span different switching hardware.

This makes programmability, SDK support and software compatibility important alongside raw terabit-per-second capacity.

The 2026 Switching Architecture in One View

AI workloads
↓
More accelerator-to-accelerator traffic
↓
800G network links
↓
Higher-density switch ASICs
↓
224G electrical signaling
↓
1.6T Ethernet development
↓
Optics, CPO and LPO integration
↓
Multi-vendor interoperability

Ethernet switch chips market is therefore being reshaped by an entire technology stack rather than by one isolated specification. Broadcom’s 102.4T Tomahawk 6, Cisco’s 102.4T Silicon One G300, NVIDIA’s 800G Spectrum platforms and the industry’s active 1.6T interoperability work demonstrate how quickly switching silicon is moving toward terabit-scale AI infrastructure.

For 2026, the important transition is not simply from one Ethernet speed to another. It is the transformation of the switch chip into a central piece of AI infrastructure where bandwidth, latency, programmability, optical integration and interoperability must advance together.