Cadence has announced a new Chiplet Spec-to-Packaged Parts ecosystem, aimed at reducing engineering complexity and accelerating time to market for customers developing chiplet-based solutions for physical AI, data centres, and high-performance computing (HPC) applications. The initiative addresses growing design challenges as multi-die architectures become essential for achieving higher performance, scalability, and cost efficiency. 

The ecosystem launches with a strong group of IP partners, including Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, alongside silicon analytics specialist proteanTecs. To further streamline customer adoption and reduce risk, Cadence is collaborating with Samsung Foundry to develop a silicon prototype demonstration on the SF5A process, integrating pre-validated partner IP. 

Deepening Cadence–Arm Collaboration for Physical AI 

Building on a long history of collaboration, Cadence and Arm are working closely to accelerate innovation across physical and infrastructure AI workloads. Cadence is leveraging advanced Arm IP, including the Arm Zena Compute Subsystem (CSS), to strengthen its Physical AI chiplet platform and Chiplet Framework. 

These solutions are designed to meet the requirements of: 

• Edge AI applications such as automotive systems, robotics, and drones 

• Infrastructure and cloud platforms, including data center and HPC deployments 

• Standards-based I/O and memory chiplets for scalable system design 

By aligning on industry standards, the partnership provides customers with a lower-risk path to advanced chiplet adoption. 

Spec-Driven Automation and Standards-Based Design 

Cadence’s ecosystem is built on spec-driven automation, enabling the generation of chiplet architectures that combine Cadence IP with third-party partner IP. These architectures incorporate chiplet management, security, and safety features, all supported by advanced software workflows. 

Key platform capabilities include: 

• Seamless simulation using the Cadence Xcelium Logic Simulator 

• Scalable emulation through the Cadence Palladium Z3 Enterprise Emulation Platform 

• Real-time feedback in physical design to accelerate place-and-route cycles 

• Compliance with Arm Chiplet System Architecture, UCIe, and emerging OCP Foundational Chiplet System Architecture standards 

The ecosystem also supports high-speed interfaces through Cadence’s protocol IP portfolio, including LPDDR6/5X, DDR5-MRDIMM, PCIe 7.0, and HBM4. 

Silicon Validation Confirms Readiness 

An earlier prototype of Cadence’s base system chiplet, which integrates the Cadence chiplet framework along with UCIe 32G and LPDDR5X IP, has already been fully silicon validated. This milestone underscores the maturity of the platform and reinforces its readiness for broader industry adoption. 

Shaping the Future of Chiplet-Based Systems 

With its Spec-to-Packaged Parts approach, Cadence is enabling customers to move from concept to production with greater confidence, flexibility, and speed. By combining pre-integrated IP, standards compliance, and proven EDA workflows, the company is helping unlock the next wave of scalable, high-performance, and AI-driven systems. 

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