Key Statistics
Key Takeaways
- Market size: 2026 USD 4,366 million, increasing to 2036 USD 15,247 million, with 13.3% compound annual growth across the 2027–2036 outlook.
- Type leadership: Redistribution CSP Substrate represents an estimated ~58% of 2026 demand; the alternative structure remains important where integration and manufacturing differ.
- Application demand: PMIC/PMU leads application revenue at an estimated ~30%; qualification differs substantially by end use.
- Geographic profile: Germany leads with an estimated ~31% share in 2026, and the five-region market model distinguishes production strength from customer demand.
- Constraint: Advanced assembly process and capex costs affects growth alongside process qualifications and competition, while small-form-factor device package integration supports product commercialization.
Europe Chip Scale Packaging Market Overview
The Europe Chip Scale Packaging market generated USD 4,366 million in the 2026 base year and is projected to reach USD 15,247 million by 2036, at a 13.3% compound annual growth rate for 2027–2036. Germany leads the 2026 regional mix with an estimated ~31% share. For Europe Chip Scale Packaging, commercial orders depend on technical qualification, recurring supply arrangements and integration with downstream customers. Product reliability and application-specific performance in Europe Chip Scale Packaging determine whether engineering approvals become contracted sales.
In Europe Chip Scale Packaging, manufacturers and qualified customers confronts Definition and customer requirements in assembly processes for near-die-size semiconductor packages combine specialized production steps with downstream application testing, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For manufacturers and qualified customers in Europe Chip Scale Packaging, the commercial effect of Definition and customer requirements in assembly is that engineering performance and contract security must advance together for semiconductor assembly; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
The the scope of commercial revenue segment of Europe Chip Scale Packaging faces Revenue covers the European commercial ecosystem for chip-scale packages at the level of packaging technologies, processing, materials and associated assembly equipment, including redistribution and molded configurations. Finished consumer products and complete vehicles are excluded; overlapping sales across materials, tools and packaging services must be reconciled when estimating the total., creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for the scope of commercial revenue, developments involving Revenue covers the European commercial ecosystem mean the boundary prevents downstream devices or entire manufacturing equipment lines being counted a second time; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Within Europe Chip Scale Packaging, manufacturers and qualified customers must manage Technical architecture and process capabilities in assembly processes for near-die-size semiconductor packages combine specialized production steps with downstream application testing, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in manufacturers and qualified customers assessing Technical architecture and process capabilities in, engineering performance and contract security must advance together for semiconductor assembly; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Market positioning for manufacturers and qualified customers in Europe Chip Scale Packaging reflects Demand mechanisms and commercial channels in assembly processes for near-die-size semiconductor packages combine specialized production steps with downstream application testing; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because Demand mechanisms and commercial channels in shapes Europe Chip Scale Packaging procurement for manufacturers and qualified customers, engineering performance and contract security must advance together for semiconductor assembly; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
In Europe Chip Scale Packaging, manufacturers and qualified customers confronts Recent investment and technology qualification in assembly processes for near-die-size semiconductor packages combine specialized production steps with downstream application testing, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For manufacturers and qualified customers in Europe Chip Scale Packaging, the commercial effect of Recent investment and technology qualification in is that engineering performance and contract security must advance together for semiconductor assembly; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Segment Analysis: By Type
The the type market segment of Europe Chip Scale Packaging faces Redistribution CSP Substrate leads at an estimated ~58% share and Molded CSP Substrate expands at a modeled ~14.4% CAGR, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for the type market, developments involving Redistribution CSP Substrate leads at an mean purchase commitments are tied to qualification, yields and product durability; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
| Type | Function | Market position |
|---|---|---|
| Redistribution CSP Substrate | In Europe Chip Scale Packaging, Redistribution CSP Substrate confronts its device or package architecture determines how wafer-level redistribution, package thickness, bump pitch and test yield are managed, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Redistribution CSP Substrate in Europe Chip Scale Packaging, the commercial effect of its device or package architecture determines is that manufacturers select the process for target semiconductor assembly costs and the application duty cycle; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. | The Redistribution CSP Substrate segment of Europe Chip Scale Packaging faces the estimated base-year revenue share is ~58%, while modeled growth is ~12.4% CAGR across the 2027–2036 horizon, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Redistribution CSP Substrate, developments involving the estimated base-year revenue share is mean competitive position depends on satisfying both unit-price and production-qualification targets; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| Molded CSP Substrate | The Molded CSP Substrate segment of Europe Chip Scale Packaging faces its device or package architecture determines how wafer-level redistribution, package thickness, bump pitch and test yield are managed, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Molded CSP Substrate, developments involving its device or package architecture determines mean manufacturers select the process for target semiconductor assembly costs and the application duty cycle; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. | Within Europe Chip Scale Packaging, Molded CSP Substrate must manage the estimated base-year revenue share is ~42%, while modeled growth is ~14.4% CAGR across the 2027–2036 horizon, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Molded CSP Substrate assessing the estimated base-year revenue share is, competitive position depends on satisfying both unit-price and production-qualification targets; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
By Country
In Europe Chip Scale Packaging, By Country confronts the secondary classification separates Germany, United Kingdom, France, Italy, Spain, Netherlands, Belgium without changing the measured revenue boundary, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For By Country in Europe Chip Scale Packaging, the commercial effect of the secondary classification separates Germany, United is that customers can interpret overlapping engineering specifications within a consistent 2026 market allocation; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
| Member | Base-year position | Commercial role |
|---|---|---|
| Germany | Estimated ~31% 2026 share | In Europe Chip Scale Packaging, Germany confronts this member has an estimated ~31% position under by country and an identifiable technical role, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Germany in Europe Chip Scale Packaging, the commercial effect of this member has an estimated ~31% is that part selection influences yield, qualification depth and commercial availability; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
| United Kingdom | Estimated ~18% 2026 share | The United Kingdom segment of Europe Chip Scale Packaging faces this member has an estimated ~18% position under by country and an identifiable technical role, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for United Kingdom, developments involving this member has an estimated ~18% mean part selection influences yield, qualification depth and commercial availability; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| France | Estimated ~20% 2026 share | Within Europe Chip Scale Packaging, France must manage this member has an estimated ~20% position under by country and an identifiable technical role, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in France assessing this member has an estimated ~20%, part selection influences yield, qualification depth and commercial availability; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
| Italy | Estimated ~7% 2026 share | Market positioning for Italy in Europe Chip Scale Packaging reflects this member has an estimated ~7% position under by country and an identifiable technical role; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because this member has an estimated ~7% shapes Europe Chip Scale Packaging procurement for Italy, part selection influences yield, qualification depth and commercial availability; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036. |
| Spain | Estimated ~7% 2026 share | In Europe Chip Scale Packaging, Spain confronts this member has an estimated ~7% position under by country and an identifiable technical role, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Spain in Europe Chip Scale Packaging, the commercial effect of this member has an estimated ~7% is that part selection influences yield, qualification depth and commercial availability; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
| Netherlands | Estimated ~10% 2026 share | The Netherlands segment of Europe Chip Scale Packaging faces this member has an estimated ~10% position under by country and an identifiable technical role, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Netherlands, developments involving this member has an estimated ~10% mean part selection influences yield, qualification depth and commercial availability; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| Belgium | Estimated ~7% 2026 share | Within Europe Chip Scale Packaging, Belgium must manage this member has an estimated ~7% position under by country and an identifiable technical role, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Belgium assessing this member has an estimated ~7%, part selection influences yield, qualification depth and commercial availability; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
Segment Analysis: By Application
The downstream procurement segment of Europe Chip Scale Packaging faces PMIC/PMU holds an estimated ~30% 2026 application share, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for downstream procurement, developments involving PMIC/PMU holds an estimated ~30% 2026 mean contract qualification links technical use cases to sustained semiconductor assembly requirements; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
| Application | Demand characteristics |
|---|---|
| Bluetooth | In Europe Chip Scale Packaging, Bluetooth confronts the application accounts for an estimated ~14% of 2026 revenue and a modeled ~14.1% CAGR, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Bluetooth in Europe Chip Scale Packaging, the commercial effect of the application accounts for an estimated is that buyers focus on application-relevant tests and repeatable component or substrate supply; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
| WLAN | The WLAN segment of Europe Chip Scale Packaging faces the application accounts for an estimated ~16% of 2026 revenue and a modeled ~15.2% CAGR, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for WLAN, developments involving the application accounts for an estimated mean buyers focus on application-relevant tests and repeatable component or substrate supply; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| PMIC/PMU | Within Europe Chip Scale Packaging, PMIC/PMU must manage the application accounts for an estimated ~30% of 2026 revenue and a modeled ~12.8% CAGR, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in PMIC/PMU assessing the application accounts for an estimated, buyers focus on application-relevant tests and repeatable component or substrate supply; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
| MOSFET | Market positioning for MOSFET in Europe Chip Scale Packaging reflects the application accounts for an estimated ~25% of 2026 revenue and a modeled ~12.9% CAGR; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because the application accounts for an estimated shapes Europe Chip Scale Packaging procurement for MOSFET, buyers focus on application-relevant tests and repeatable component or substrate supply; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036. |
| Camera | In Europe Chip Scale Packaging, Camera confronts the application accounts for an estimated ~15% of 2026 revenue and a modeled ~11.9% CAGR, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Camera in Europe Chip Scale Packaging, the commercial effect of the application accounts for an estimated is that buyers focus on application-relevant tests and repeatable component or substrate supply; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
Within Europe Chip Scale Packaging, OEM channels must manage demand from Bluetooth, WLAN, PMIC/PMU moves through direct sourcing, integrators and qualified specialist suppliers, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in OEM channels assessing demand from Bluetooth, WLAN, PMIC/PMU moves, channel partners who maintain documentation and local engineering contacts retain more repeat orders; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Regional Analysis
In Europe Chip Scale Packaging, the five demand geographies confronts Germany commands an estimated ~31% of market revenue and the next regions account for ~20% and ~18% in 2026, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For the five demand geographies in Europe Chip Scale Packaging, the commercial effect of Germany commands an estimated ~31% of is that supplier selection reflects technological capabilities as well as country-by-country procurement and supply-chain rules; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Which geographic markets have the strongest demand, and what drives the differences?
The geographic distribution segment of Europe Chip Scale Packaging faces growth ranges among analyzed territories and production centres, with modeled regional rates disclosed next to each estimated 2026 share, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for geographic distribution, developments involving growth ranges among analyzed territories and mean the global revenue allocation remains consistent with the anchored market forecast; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
| Region | Position | Growth outlook | Demand profile | What decides supplier selection |
|---|---|---|---|---|
| Germany | Largest (~31% share in 2026) | ~12.9% CAGR 2027–2036 | The Germany segment of Europe Chip Scale Packaging faces automotive electronics and integrated circuit production contribute to a modeled ~31% 2026 share, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Germany, developments involving automotive electronics and integrated circuit production mean qualified demand is driven by application-specific electronics investment; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. | Within Europe Chip Scale Packaging, Germany must manage wafer-level redistribution, package thickness, bump pitch and test yield are important selection variables, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Germany assessing wafer-level redistribution, package thickness, bump pitch, suppliers must support local qualification and logistics; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
| France | Market (~20% share in 2026) | ~14.4% CAGR 2027–2036 | Within Europe Chip Scale Packaging, France must manage panel-level technology and heterogeneous integrated devices contribute to a modeled ~20% 2026 share, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in France assessing panel-level technology and heterogeneous integrated devices, qualified demand is driven by application-specific electronics investment; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. | Market positioning for France in Europe Chip Scale Packaging reflects wafer-level redistribution, package thickness, bump pitch and test yield are important selection variables; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because wafer-level redistribution, package thickness, bump pitch shapes Europe Chip Scale Packaging procurement for France, suppliers must support local qualification and logistics; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036. |
| United Kingdom | Market (~18% share in 2026) | ~12.4% CAGR 2027–2036 | Market positioning for United Kingdom in Europe Chip Scale Packaging reflects sensor modules and RF semiconductor design contribute to a modeled ~18% 2026 share; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because sensor modules and RF semiconductor design shapes Europe Chip Scale Packaging procurement for United Kingdom, qualified demand is driven by application-specific electronics investment; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036. | In Europe Chip Scale Packaging, United Kingdom confronts wafer-level redistribution, package thickness, bump pitch and test yield are important selection variables, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For United Kingdom in Europe Chip Scale Packaging, the commercial effect of wafer-level redistribution, package thickness, bump pitch is that suppliers must support local qualification and logistics; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
| Benelux | Market (~17% share in 2026) | ~14.9% CAGR 2027–2036 | In Europe Chip Scale Packaging, Benelux confronts interconnect research, electronic packaging equipment and test contribute to a modeled ~17% 2026 share, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Benelux in Europe Chip Scale Packaging, the commercial effect of interconnect research, electronic packaging equipment and is that qualified demand is driven by application-specific electronics investment; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. | The Benelux segment of Europe Chip Scale Packaging faces wafer-level redistribution, package thickness, bump pitch and test yield are important selection variables, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Benelux, developments involving wafer-level redistribution, package thickness, bump pitch mean suppliers must support local qualification and logistics; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| Southern Europe | Market (~14% share in 2026) | ~11.9% CAGR 2027–2036 | The Southern Europe segment of Europe Chip Scale Packaging faces medical electronics, vehicle power systems and outsourced assembly contribute to a modeled ~14% 2026 share, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Southern Europe, developments involving medical electronics, vehicle power systems and mean qualified demand is driven by application-specific electronics investment; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. | Within Europe Chip Scale Packaging, Southern Europe must manage wafer-level redistribution, package thickness, bump pitch and test yield are important selection variables, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Southern Europe assessing wafer-level redistribution, package thickness, bump pitch, suppliers must support local qualification and logistics; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
Key Europe Chip Scale Packaging Manufacturers and Competitive Landscape
In Europe Chip Scale Packaging, producers and technology integrators confronts the profiled companies range from suppliers of assembly processes for near-die-size semiconductor packages to device makers, end customers and equipment providers, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For producers and technology integrators in Europe Chip Scale Packaging, the commercial effect of the profiled companies range from suppliers is that accurate commercial positioning requires keeping supplier roles separate rather than treating every named company as an identical product vendor; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
In Europe Chip Scale Packaging, STMicroelectronics confronts the company participates in the broader ecosystem through technology development, device integration, fabrication or customer procurement, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For STMicroelectronics in Europe Chip Scale Packaging, the commercial effect of the company participates in the broader is that it influences design-in cycles but its total enterprise revenue cannot be equated with the narrowly defined product market; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
The Infineon Technologies segment of Europe Chip Scale Packaging faces the company participates in the broader ecosystem through technology development, device integration, fabrication or customer procurement, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Infineon Technologies, developments involving the company participates in the broader mean it influences design-in cycles but its total enterprise revenue cannot be equated with the narrowly defined product market; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Within Europe Chip Scale Packaging, NXP Semiconductors must manage the company participates in the broader ecosystem through technology development, device integration, fabrication or customer procurement, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in NXP Semiconductors assessing the company participates in the broader, it influences design-in cycles but its total enterprise revenue cannot be equated with the narrowly defined product market; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Market positioning for AMS AG in Europe Chip Scale Packaging reflects the company participates in the broader ecosystem through technology development, device integration, fabrication or customer procurement; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because the company participates in the broader shapes Europe Chip Scale Packaging procurement for AMS AG, it influences design-in cycles but its total enterprise revenue cannot be equated with the narrowly defined product market; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
Tier structure
| Tier | Companies | Basis of competition |
|---|---|---|
| Tier 1 | STMicroelectronics, Infineon Technologies, NXP Semiconductors | In Europe Chip Scale Packaging, core commercial leaders confronts several suppliers maintain repeat production and application engineering coverage for assembly processes for near-die-size semiconductor packages, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For core commercial leaders in Europe Chip Scale Packaging, the commercial effect of several suppliers maintain repeat production and is that multi-site customer qualification and reliable production capacity support broader market coverage; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036. |
| Tier 2 | AMS AG, ASE Group, Chipbond Technology Corporation | The specialists and regional producers segment of Europe Chip Scale Packaging faces qualification, package architecture and process expertise are relevant for narrower use cases in semiconductor assembly, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for specialists and regional producers, developments involving qualification, package architecture and process expertise mean specialised supply and responsiveness can offset smaller corporate scale; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements. |
| Adjacent ecosystem | JCET Group, ASM Pacific Technology, Siliconware Precision Industries, Nanium S.A. | Within Europe Chip Scale Packaging, system makers, materials groups and specialist technology firms must manage the profiled list includes companies with different degrees of exposure to assembly processes for near-die-size semiconductor packages, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in system makers, materials groups and specialist technology firms assessing the profiled list includes companies with, roles in technology or distribution are distinguished from confirmed independent sales of the market product; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036. |
Key companies profiled
- STMicroelectronics
- Infineon Technologies
- NXP Semiconductors
- AMS AG
- ASE Group
- Chipbond Technology Corporation
- JCET Group
- ASM Pacific Technology
- Siliconware Precision Industries
- Nanium S.A.
Production Capacity Analysis
In Europe Chip Scale Packaging, fabrication and assembly capacity confronts semiconductor assembly is constrained by qualified processes rather than nominal factory floor area alone, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For fabrication and assembly capacity in Europe Chip Scale Packaging, the commercial effect of semiconductor assembly is constrained by qualified is that vendors that demonstrate stable lot-to-lot characteristics are better positioned to supply customers from 2027 onward; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
In Europe Chip Scale Packaging, current manufacturing networks confronts the primary sources describe semiconductor assembly facilities, production programs and specialized process technologies, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For current manufacturing networks in Europe Chip Scale Packaging, the commercial effect of the primary sources describe semiconductor assembly is that capacity expansion improves supply only after capability, test and reliability qualifications; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
The cross-border supply segment of Europe Chip Scale Packaging faces component and equipment inputs arrive through suppliers with different export, energy and transport exposures, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for cross-border supply, developments involving component and equipment inputs arrive through mean dual-qualified materials and alternative routes offer resilience to multi-year demand; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Within Europe Chip Scale Packaging, upstream process constraints must manage wafer-level redistribution, package thickness, bump pitch and test yield impose yield and engineering limits on manufacturing output, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in upstream process constraints assessing wafer-level redistribution, package thickness, bump pitch, factory throughput does not always translate directly into marketable finished units; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Market Dynamics
In Europe Chip Scale Packaging, growth and constraint factors confronts customer demand for assembly processes for near-die-size semiconductor packages is shaped by small-form-factor device package integration, qualification and supply-chain resilience, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For growth and constraint factors in Europe Chip Scale Packaging, the commercial effect of customer demand for assembly processes for is that the opposing forces are considered across three successive forecast windows instead of being treated as equal through the entire period; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
MARKET DRIVERS
Drivers Impact Analysis*
| Market Drivers | Impact Rank | CAGR Contribution (%) | 2027–2029 | 2030–2032 | 2033–2036 |
|---|---|---|---|---|---|
| Small-form-factor device package integration | High | +5.61% | High | Medium | Low |
| European automotive semiconductor demand | High | +4.34% | Medium | Low | High |
| Wireless sensor and power-management requirements | Medium-High | +3.26% | Low | High | Medium |
| Regional investments in advanced packaging | Medium | +2.35% | High | Medium | Low |
| Panel-level and fan-out package productivity | Low-Medium | +1.63% | Medium | Low | High |
| Others (application diversification, factory learning, integration support, supplier partnerships) | Low | +0.90% | Low | High | Medium |
Small-form-factor device package integration
In Europe Chip Scale Packaging, Small-form-factor device package integration confronts small-form-factor device package integration affects purchasing specifications and the rate at which customers qualify assembly processes for near-die-size semiconductor packages, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Small-form-factor device package integration in Europe Chip Scale Packaging, the commercial effect of small-form-factor device package integration affects purchasing is that future contracts increasingly reward test capacity and documented delivery reliability; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
European automotive semiconductor demand
The European automotive semiconductor demand segment of Europe Chip Scale Packaging faces european automotive semiconductor demand affects purchasing specifications and the rate at which customers qualify assembly processes for near-die-size semiconductor packages, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for European automotive semiconductor demand, developments involving european automotive semiconductor demand affects purchasing mean future contracts increasingly reward test capacity and documented delivery reliability; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Wireless sensor and power-management requirements
Within Europe Chip Scale Packaging, Wireless sensor and power-management requirements must manage wireless sensor and power-management requirements affects purchasing specifications and the rate at which customers qualify assembly processes for near-die-size semiconductor packages, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Wireless sensor and power-management requirements assessing wireless sensor and power-management requirements affects, future contracts increasingly reward test capacity and documented delivery reliability; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Regional investments in advanced packaging
Market positioning for Regional investments in advanced packaging in Europe Chip Scale Packaging reflects regional investments in advanced packaging affects purchasing specifications and the rate at which customers qualify assembly processes for near-die-size semiconductor packages; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because regional investments in advanced packaging affects shapes Europe Chip Scale Packaging procurement for Regional investments in advanced packaging, future contracts increasingly reward test capacity and documented delivery reliability; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
MARKET RESTRAINTS
Restraints Impact Analysis*
| Market Restraints | Impact Rank | CAGR Contribution (%) | 2027–2029 | 2030–2032 | 2033–2036 |
|---|---|---|---|---|---|
| Advanced assembly process and capex costs | High | -2.30% | High | Medium | Low |
| Materials qualification and packaging reliability | Medium-High | -1.44% | Medium | Low | High |
| Regional labor and compliance costs | Medium | -0.72% | Low | High | Medium |
| Others (working-capital exposure, extended customer qualification, competing technologies) | Low | -0.33% | High | Medium | Low |
Advanced assembly process and capex costs
In Europe Chip Scale Packaging, Advanced assembly process and capex costs confronts advanced assembly process and capex costs creates uncertainty during manufacturing, deployment or customer approval, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Advanced assembly process and capex costs in Europe Chip Scale Packaging, the commercial effect of advanced assembly process and capex costs is that operations planning and second-source qualification can partly moderate the constraint; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Materials qualification and packaging reliability
The Materials qualification and packaging reliability segment of Europe Chip Scale Packaging faces materials qualification and packaging reliability creates uncertainty during manufacturing, deployment or customer approval, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Materials qualification and packaging reliability, developments involving materials qualification and packaging reliability creates mean operations planning and second-source qualification can partly moderate the constraint; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Regional labor and compliance costs
Within Europe Chip Scale Packaging, Regional labor and compliance costs must manage regional labor and compliance costs creates uncertainty during manufacturing, deployment or customer approval, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Regional labor and compliance costs assessing regional labor and compliance costs creates, operations planning and second-source qualification can partly moderate the constraint; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Price competition and lengthy product qualification
Market positioning for Price competition and lengthy product qualification in Europe Chip Scale Packaging reflects price competition and lengthy product qualification creates uncertainty during manufacturing, deployment or customer approval; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because price competition and lengthy product qualification shapes Europe Chip Scale Packaging procurement for Price competition and lengthy product qualification, operations planning and second-source qualification can partly moderate the constraint; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
MARKET OPPORTUNITIES
Advanced process integration
In Europe Chip Scale Packaging, Advanced process integration confronts advanced process integration provides an application opportunity across the supply chain, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Advanced process integration in Europe Chip Scale Packaging, the commercial effect of advanced process integration provides an application is that suppliers can expand design wins by balancing technical performance, support and delivery assurance; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Long-term automotive and industrial qualifications
The Long-term automotive and industrial qualifications segment of Europe Chip Scale Packaging faces long-term automotive and industrial qualifications provides an application opportunity across the supply chain, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Long-term automotive and industrial qualifications, developments involving long-term automotive and industrial qualifications provides mean suppliers can expand design wins by balancing technical performance, support and delivery assurance; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Specialised sensing and device performance
Within Europe Chip Scale Packaging, Specialised sensing and device performance must manage specialised sensing and device performance provides an application opportunity across the supply chain, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Specialised sensing and device performance assessing specialised sensing and device performance provides, suppliers can expand design wins by balancing technical performance, support and delivery assurance; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Geographically diversified commercial supply
Market positioning for Geographically diversified commercial supply in Europe Chip Scale Packaging reflects geographically diversified commercial supply provides an application opportunity across the supply chain; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because geographically diversified commercial supply provides an shapes Europe Chip Scale Packaging procurement for Geographically diversified commercial supply, suppliers can expand design wins by balancing technical performance, support and delivery assurance; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
Supply Chain Analysis
In Europe Chip Scale Packaging, the manufacturing and distribution chain confronts assembly processes for near-die-size semiconductor packages depend on successive raw materials, controlled processing, integration and downstream device qualification, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For the manufacturing and distribution chain in Europe Chip Scale Packaging, the commercial effect of assembly processes for near-die-size semiconductor packages is that each transition can delay commercialization despite upstream nameplate capacity; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Upstream. In Europe Chip Scale Packaging, Upstream confronts material characteristics defines a distinct transfer of responsibility in the supply chain, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For Upstream in Europe Chip Scale Packaging, the commercial effect of material characteristics defines a distinct transfer is that traceability and engineering feedback improve the probability of reliable repeat orders; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
Manufacturing. The Manufacturing segment of Europe Chip Scale Packaging faces lot-level process stability defines a distinct transfer of responsibility in the supply chain, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Manufacturing, developments involving lot-level process stability defines a distinct mean traceability and engineering feedback improve the probability of reliable repeat orders; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Channel. Within Europe Chip Scale Packaging, Channel must manage customer and distributor qualifications defines a distinct transfer of responsibility in the supply chain, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Channel assessing customer and distributor qualifications defines a, traceability and engineering feedback improve the probability of reliable repeat orders; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Downstream. Market positioning for Downstream in Europe Chip Scale Packaging reflects application integration and lifecycle support defines a distinct transfer of responsibility in the supply chain; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because application integration and lifecycle support defines shapes Europe Chip Scale Packaging procurement for Downstream, traceability and engineering feedback improve the probability of reliable repeat orders; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
Recent Developments in Europe Chip Scale Packaging
- 2 July 2026 Announced
Infineon opened its five-billion-euro Smart Power Fab in Dresden to produce power and analog semiconductor devices for industrial, vehicle and data-center applications For the Europe Chip Scale Packaging sector, The factory strengthens European device manufacturing capacity and creates a credible downstream customer environment for advanced packaging qualification, without implying that all fab investment is chip-scale package revenue. For the Europe Chip Scale Packaging industry, the announcement dated 2 July 2026 requires customer-specific qualification before repeat commercial orders materialize. Source - 2 March 2026 Published
imec announced access to fine-pitch redistribution layer and die-to-wafer hybrid bonding design kits through the NanoIC pilot line For the Europe Chip Scale Packaging sector, The Belgian initiative lets researchers and companies explore high-density chip interconnection, which can improve development pathways for European semiconductor package and substrate technologies. For the Europe Chip Scale Packaging industry, the announcement dated 2 March 2026 requires customer-specific qualification before repeat commercial orders materialize. Source - 25 September 2025 Announced
ASMPT and KOKUSAI ELECTRIC disclosed a joint development agreement on hybrid bonding and thermo-compression bonding For the Europe Chip Scale Packaging sector, Improved bond alignment and process integration can broaden the set of devices that designers consider for high-density packages, while commercial qualification determines when those tools affect delivered package output. For the Europe Chip Scale Packaging industry, the announcement dated 25 September 2025 requires customer-specific qualification before repeat commercial orders materialize. Source - 17 September 2025 Announced
STMicroelectronics described a sixty-million-dollar panel-level packaging pilot-line investment in Tours, France, with operation expected during the third quarter of 2026 For the Europe Chip Scale Packaging sector, The initiative demonstrates direct European industrial activity in packaging process development and offers a localized path for higher-throughput assembly learning. For the Europe Chip Scale Packaging industry, the announcement dated 17 September 2025 requires customer-specific qualification before repeat commercial orders materialize. Source - 3 September 2025 Announced
ASMPT joined the JOINT3 panel interposer development consortium, whose platform works with large organic panels and related assembly materials For the Europe Chip Scale Packaging sector, The collaboration addresses equipment and process compatibility for future package manufacturing; its immediate significance is technical development, rather than independently verified full commercial capacity. For the Europe Chip Scale Packaging industry, the announcement dated 3 September 2025 requires customer-specific qualification before repeat commercial orders materialize. Source - 26 June 2025 Published
ASE published research on moving fan-out packaging from wafer-level processes toward panel-level manufacturing For the Europe Chip Scale Packaging sector, The work identifies carrier utilization and process warpage as practical manufacturing variables, informing potential cost and yield tradeoffs for package designers considering advanced redistribution and substrate configurations. For the Europe Chip Scale Packaging industry, the announcement dated 26 June 2025 requires customer-specific qualification before repeat commercial orders materialize. Source
REPORT SCOPE & SEGMENTATION
| Attribute | Details |
|---|---|
| Study Period | 2021–2036 |
| Base Year | 2026 |
| Estimated Year | 2027 |
| Forecast Year | 2036 |
| Historical Period | 2021–2025 |
| 2026 Market Size | USD 4,366 million |
| 2027 Market Estimate | USD 4,948 million |
| 2036 Market Size | USD 15,247 million |
| CAGR (2027–2036) | 13.3% |
| Units | Revenue in USD million |
| By Type | Redistribution CSP Substrate · Molded CSP Substrate |
| By Application | Bluetooth · WLAN · PMIC/PMU · MOSFET · Camera |
| By Country | Germany · United Kingdom · France · Italy · Spain · Netherlands · Belgium |
| By Region | Five analytical demand regions within the geographic revenue scope; estimated regional shares represent 2026 revenue and total 100%. GermanyDresden, Munich, Saxony FranceTours, Crolles, Grenoble United KingdomCambridge, Bristol, Southampton BeneluxLeuven, Eindhoven, the Netherlands Southern EuropeItaly, Spain, Portugal |
| Key Companies Profiled | STMicroelectronics, Infineon Technologies, NXP Semiconductors, AMS AG, ASE Group, Chipbond Technology Corporation, JCET Group, ASM Pacific Technology, Siliconware Precision Industries, Nanium S.A. |
| Customization Scope | Custom country estimates, application splits, component architectures and supplier comparisons are available for the 2026–2036 planning horizon. |
Frequently Asked Questions
What is the market size of Europe Chip Scale Packaging?
The Europe Chip Scale Packaging market generated USD 4,366 million in the 2026 base year and is forecast to reach USD 15,247 million in 2036 at a 13.3% compound annual growth rate. For Europe Chip Scale Packaging, the monetary forecast follows the published endpoints and the specified workbook year window. Demand reflects purchase of assembly processes for near-die-size semiconductor packages rather than revenue from unrelated completed electronic systems, and actual sourcing depends on commercial qualification and supply capability.
Which product type leads Europe Chip Scale Packaging?
The Redistribution CSP Substrate segment of Europe Chip Scale Packaging faces this leading type has estimated ~58% share of base-year revenue, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for Redistribution CSP Substrate, developments involving this leading type has estimated ~58% mean design wins still depend on application qualifications and stable manufacturing yields; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
What is the fastest-growing type in this market?
Within Europe Chip Scale Packaging, Molded CSP Substrate must manage this type shows a modeled ~14.4% CAGR and an estimated ~42% share, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Molded CSP Substrate assessing this type shows a modeled ~14.4%, its growth is connected to integration requirements rather than automatic conversion of all product demand; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Which application is the largest demand category?
Market positioning for PMIC/PMU in Europe Chip Scale Packaging reflects this application has an estimated ~30% revenue share; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because this application has an estimated ~30% shapes Europe Chip Scale Packaging procurement for PMIC/PMU, qualifications and procurement channels remain distinct across device categories; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
Which application requires specialist qualification?
The WLAN segment of Europe Chip Scale Packaging faces the modeled 2026 share is ~16% and growth is ~15.2% CAGR, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for WLAN, developments involving the modeled 2026 share is ~16% mean customer-specific electrical, mechanical or optical validation shapes supplier choice; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
Which regional market leads in the base year?
Within Europe Chip Scale Packaging, Germany must manage the largest geography has an estimated ~31% 2026 share, making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in Germany assessing the largest geography has an estimated, production concentration and local demand work together rather than being interchangeable quantities; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
How quickly does the leading region grow?
Market positioning for Germany in Europe Chip Scale Packaging reflects the region advances at modeled ~12.9% CAGR across the 2027–2036 forecast; buyers expect verified wafer-level redistribution, package thickness, bump pitch and test yield and a route from samples to production. Because the region advances at modeled ~12.9% shapes Europe Chip Scale Packaging procurement for Germany, local capital projects and qualification decisions influence the realized rate; vendor capability, delivery schedules, process yields and field support influence the conversion of these requirements into revenue through 2036.
What are the most important market drivers?
In Europe Chip Scale Packaging, the market drivers confronts small-form-factor device package integration and european automotive semiconductor demand shape demand, so commercial suppliers qualify wafer-level redistribution, package thickness, bump pitch and test yield through manufacturing controls and application-level tests. For the market drivers in Europe Chip Scale Packaging, the commercial effect of small-form-factor device package integration and european is that applications benefit only once products have manufacturing and field qualification evidence; buyers also assess supply assurance, engineering support and customer milestones before scaling repeat orders through 2036.
What supply and cost restraints affect manufacturers?
The suppliers and buyers segment of Europe Chip Scale Packaging faces advanced assembly process and capex costs combines with materials qualification and packaging reliability, creating requirements for wafer-level redistribution, package thickness, bump pitch and test yield, process stability and contract documentation. In the Europe Chip Scale Packaging procurement setting for suppliers and buyers, developments involving advanced assembly process and capex costs mean contracting and inventory policy therefore matter alongside pure technical design; industrial purchasers evaluate product reliability, customer approval and 2027–2036 supply arrangements.
What products and geographies are included in market scope?
Within Europe Chip Scale Packaging, the scope definition must manage Revenue covers the European commercial ecosystem for chip-scale packages at the level of packaging technologies, processing, materials and associated assembly equipment, including redistribution and molded configurations. Finished consumer products and complete vehicles are excluded; overlapping sales across materials, tools and packaging services must be reconciled when estimating the total., making wafer-level redistribution, package thickness, bump pitch and test yield central to supplier qualification and delivery consistency. For customers of Europe Chip Scale Packaging in the scope definition assessing Revenue covers the European commercial ecosystem, this preserves consistent totals across type, application and geographic allocations; mature manufacturing, test evidence, application integration and stable technical support influence awards through 2036.
Research Sources & Evidence Base
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